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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 19364 rev: a amendment/ +3 issue date: september 1996 AM79C961A pcnet -isa ii jumperless, full duplex single-chip ethernet controller for isa distinctive characteristics n single-chip ethernet controller for the industry standard architecture (isa) and extended industry standard architecture (eisa) buses n supports ieee 802.3/ansi 8802-3 and ethernet standards n supports full duplex operation on the 10base-t, aui, and gpsi ports n direct interface to the isa or eisa bus n pin compatible to am79c961 pcnet-isa + jumperless single-chip ethernet controller n software compatible with amds am7990 lance register and descriptor architecture n low power, cmos design with sleep mode allows reduced power consumption for critical battery powered applications n individual 136-byte transmit and 128-byte receive fifos provide packet buffering for increased system latency, and support the following features: automatic retransmission with no fifo reload automatic receive stripping and transmit padding (individually programmable) automatic runt packet rejection automatic deletion of received collision frames n dynamic transmit fcs generation programmable on a frame-by-frame basis n single +5 v power supply n internal/external loopback capabilities n supports 8k, 16k, 32k, and 64k boot proms or flash for diskless node applications n supports microsofts plug and play system con?uration for jumperless designs n supports staggered at bus drive for reduced noise and ground bounce n supports 8 interrupts on chip n look ahead packet processing (lapp) allows protocol analysis to begin before end of receive frame n supports 4 dma channels on chip n supports 16 i/o locations n supports 16 boot prom locations n provides integrated attachment unit interface (aui) and 10base-t transceiver with 2 modes of port selection: automatic selection of aui or 10base-t software selection of aui or 10base-t n automatic twisted pair receive polarity detection and automatic correction of the receive polarity n supports bus-master, programmed i/o, and shared-memory architectures to ? in any pc application n supports edge and level-sensitive interrupts n dma buffer management unit for reduced cpu intervention which allows higher throughput by by-passing the platform dma n jtag boundary scan (ieee 1149.1) test access port interface for board level production test n integrated manchester encoder/decoder n supports the following types of network interfaces: aui to external 10base2, 10base5, 10base-t or 10base-f mau internal 10base-t transceiver with smart squelch to twisted pair medium n supports lance general purpose serial interface (gpsi) n 132-pin pqfp package
2 AM79C961A preliminary general description the pcnet-isa ii controller, a single-chip ethernet con- troller, is a highly integrated system solution for the pc-at industry standard architecture (isa) architec- ture. it is designed to provide ?xibility and compatibil- ity with any existing pc application. this highly integrated 132-pin vlsi device is speci?ally designed to reduce parts count and cost, and addresses applica- tions where higher system throughput is desired. the pcnet-isa ii controller is fabricated with amds advanced low-power cmos process to provide low standby current for power sensitive applications. the pcnet-isa ii controller can be con?ured into one of three different architecture modes to suit a particular pc application. in the bus master mode, all transfers are performed using the integrated dma controller. this conguration enhances system performance by allowing the pcnet-isa ii controller to bypass the plat- form dma controller and directly address the full 24-bit memory space. the implementation of bus master mode allows minimum parts count for the majority of pc applications. the pcnet-isa ii can also be con?- ured as a bus slave with either a shared memory or programmed i/o architecture for compatibility with low-end machines, such as pc/xts that do not support bus masters, and high-end machines that require local packet buffering for increased system latency. the pcnet-isa ii controller is designed to directly inter- face with the isa or eisa system bus. it contains an isa plug and play bus interface unit, dma buffer man- agement unit, 802.3 media access control function, individual 136-byte transmit and 128-byte receive fifos, ieee 802.3 de?ed attachment unit interface (aui), and a twisted pair transceiver media attach- ment unit. full duplex network operation can be enabled on any of the devices network ports. the pcnet-isa ii controller is also register compatible with the lance (am7990) ethernet controller and pcnet-isa. the dma buffer management unit sup- ports the lance descriptor software model. external remote boot and ethernet physical address proms and electrically erasable proms are also supported. this advanced ethernet controller has the built-in capability of automatically selecting either the aui port or the twisted pair transceiver. only one interface is active at any one time. the individual 136-byte transmit and 128-byte receive fifos optimize system over- head, providing suf?ient latency during packet trans- mission and reception, and minimizing intervention during normal network error recovery. the integrated manchester encoder/decoder eliminates the need for an external serial interface adapter (sia) in the node system. if support for an external encoding/decoding scheme is desired, the embedded general purpose serial interface (gpsi) allows direct access to/from the mac. in addition, the device provides programmable on-chip led drivers for transmit, receive, collision, receive polarity, link integrity and activity, or jabber status. the pcnet-isa ii controller also provides an external address detection interface tm (eadi tm ) to allow external hardware address ?tering in internet- working applications. related products part no. description am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex + ) am7996 ieee 802.3/ethernet/cheapernet transceiver am79c981 integrated multiport repeater plus ? (imr +? ) am79c987 hardware implemented management information base ? (himib ? ) am79c940 media access controller for ethernet (mace ? ) am79c90 cmos local area network controller for ethernet (c-lance) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa jumperless single-chip ethernet controller (for isa bus) am79c965 pcnet-32 single-chip 32-bit ethernet controller (for 386, 486, vl local buses) am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c974 pcnet-scsi combination single-chip ethernet and scsi controller (for pci bus)
AM79C961A 3 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. AM79C961A k c \w alternate packaging option \w=trimmed and formed (pqb132) optional processing blank=standard processing temperature range c=commercial (0 c to +70 c) package type (per prod. nomenclature/16-038) k=molded carrier ring plastic quad flat pack (pqb132) speed not applicable device number/description AM79C961A pcnet-isa ii jumperless single-chip ethernet controller for isa valid combinations AM79C961A kc, kc\w
4 AM79C961A preliminary table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block diagram: bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 connection diagram: bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 pin designations: bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 listed by pin group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 pin descriptions: bus master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ieee p996 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 isa interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 board interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 plug and play isa card state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 block diagram: bus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 connection diagrams: bus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 pin designations: bus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 listed by pin name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 listed by group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 pin descriptions: bus slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 isa interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 pin descriptions: network interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 aui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 twisted pair interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 pin descriptions: power supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 connection diagram (tqfp 144). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 pin descriptions: bus master mode (tqfp 144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 listed by pin name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 pin descriptions: bus slave (pio and shared memory) modes (tqfp 144) . . . . . . . . . . . .34 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 listed by pin name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 important note about the eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 plug and play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 auto-configuration ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 initiation key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 isolation protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 hardware protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 software protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 plug and play card control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 plug and play logical device configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . .45 detailed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 amd device driver compatible eeprom byte map . . . . . . . . . . . . . . . . . . . . . . . . . . .48 plug and play register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 pcnet-isa iis legacy bit feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 p lug & play register locations detailed description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 vendor defined byte (pnp 0xf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 checksum failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 use without eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 external scan chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AM79C961A 5 preliminary flash prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 optional ieee address prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 eisa configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 dma transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 1. initialization block dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2. descriptor dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3. fifo dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 buffer management unit (bmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 descriptor rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 descriptor rings access mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 transmit descriptor table entry (tdte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 receive descriptor table entry (rdte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 media access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 transmit and receive message data encapsulation. . . . . . . . . . . . . . . . . . . . . . . .61 manchester encoder/decoder (mendec). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 external crystal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 external clock drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 mendec transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 transmitter timing and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 input signal conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 clock acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 pll tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 carrier tracking and end of message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 data decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 differential input terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 collision detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 jitter tolerance definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 attachment unit interface (aui) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 twisted pair transceiver (t-mau) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 twisted pair transmit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 twisted pair receive function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 link test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 polarity detection and reversal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 twisted pair interface status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 collision detect function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 signal quality error (sqe) test (heartbeat) function . . . . . . . . . . . . . . . . . . . . .69 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 full duplex operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 eadi (external address detection interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 gpsi (general purpose serial interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 ieee 1149.1 test access port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 boundary scan circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 tap fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 supported instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 instruction register and decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 boundary scan register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 other data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 access operations (software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6 AM79C961A preliminary i/o resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 i/o register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 ieee address access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 boot prom access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 static ram access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 bus cycles (hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 address prom cycles external prom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 address prom cycles using eeprom data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 ethernet controller register cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 transmit operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 transmit function programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 automatic pad generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 transmit fcs generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 transmit exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 receive function programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 automatic pad stripping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 receive fcs checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 receive exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 magic packet operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 magic packet mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 magic packet receive indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 pcnet-isa ii controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 register access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 rap: register address port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 csr0: pcnet-isa ii controller status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 csr1: iadr[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 csr2: iadr[23:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 csr3: interrupt masks and deferral control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 csr4: test and features control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 csr5: control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 csr6: rcv/xmt descriptor table length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 csr8: logical address filter, ladrf[15:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 csr9: logical address filter, ladrf[31:16]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 csr10: logical address filter, ladrf[47:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 csr11: logical address filter, ladrf[63:48]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 csr12: physical address register, padr[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 csr13: physical address register, padr[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 csr14: physical address register, padr[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 csr15: mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 csr16: initialization block address lower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 csr17: initialization block address upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 csr18-19: current receive buffer address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 csr20-21: current transmit buffer address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 csr22-23: next receive buffer address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr24-25: base address of receive ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr26-27: next receive descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr28-29: current receive descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr30-31: base address of transmit ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr32-33: next transmit descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr34-35: current transmit descriptor address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr36-37: next next receive descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr38-39: next next transmit descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 csr40-41: current receive status and byte count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
AM79C961A 7 preliminary csr42-43: current transmit status and byte count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr44-45: next receive status and byte count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr46: poll time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr47: polling interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr48-49: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr50-51: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 csr52-53: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr54-55: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr56-57: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr58-59: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr60-61: previous transmit descriptor address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr62-63: previous transmit status and byte count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr64-65: next transmit buffer address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr66-67: next transmit status and byte count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 csr70-71: temporary storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr72: receive ring counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr74: transmit ring counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr76: receive ring length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr78: transmit ring length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr80: burst and fifo threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 csr82: bus activity timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 csr84-85: dma address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 csr86: buffer byte counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 csr88-89: chip id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 csr92: ring length conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 csr94: transmit time domain re?ctometry count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 csr96-97: bus interface scratch register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr98-99: bus interface scratch register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr104-105: swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr108-109: buffer management scratch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr112: missed frame count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr114: receive collision count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 csr124: buffer management unit test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 isa bus configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 isacsr0: master mode read active/sram data port . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 isacsr1: master mode write active/sram address pointer . . . . . . . . . . . . . . . . . . . . . . .104 isacsr2: miscellaneous con?uration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 isacsr3: eeprom con?uration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 isacsr4: led0 status (link integrity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 isacsr5: led1 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 isacsr6: led2 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 isacsr7: led3 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 isacsr8: software con?uration register (read-only register) . . . . . . . . . . . . . . . . . . . .110 isacsr9: miscellaneous con?uration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 initialization block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 rlen and tlen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 rdra and tdra. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 ladrf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 padr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 receive descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 rmd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 rmd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 rmd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 rmd3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 transmit descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 tmd0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 tmd1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
8 AM79C961A preliminary tmd2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 tmd3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 ethernet controller registers (accessed via rdp port) . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 isacsr?sa bus con?uration registers (accessed via idp port). . . . . . . . . . . . . . . . . .118 system application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 isa bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 compatibility considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 shared memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 optional address prom interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 boot prom interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 static ram interface (for shared memory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 aui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10base-t interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 commercial (c) devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 dc characteristics over commercial operating ranges . . . . . . . . . . . . . . . . . . . . . . . .124 switching characteristics: bus master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 switching characteristics: bus master mode?lash read cycle . . . . . . . . . . . . . . . . .130 switching characteristics: bus master mode?lash write cycle . . . . . . . . . . . . . . . .130 switching characteristics: shared memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 switching characteristics: shared memory mode?lash read cycle. . . . . . . . . . . . .134 switching characteristics: shared memory mode?lash write cycle . . . . . . . . . . . .134 switching characteristics: eadi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 switching characteristics: jtag (ieee 1149.1) interface. . . . . . . . . . . . . . . . . . . . . . . . . . . .135 switching characteristics: gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 switching characteristics: aui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 switching characteristics: 10base-t interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 switching characteristics: serial eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 switching test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 switching waveforms: bus master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 switching waveforms: shared memory mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 switching waveforms: gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 switching waveforms: eadi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 switching waveforms: jtag (ieee 1149.1) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 switching waveforms: aui. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 switching waveforms: 10base-t interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 pqb132 plastic quad flat pack trimmed and formed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 pqb132 molded carrier ring plastic quad flat pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 appendix a: pcnet-ii compatible media interface modules. . . . . . . . . . . . . . . . . . . . . . . .172 pcnet-isa ii compatible 10base-t filters and transformers . . . . . . . . . . . . . . . . . . . . . . . .172 pcnet-isa ii compatible aui isolation transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 pcnet-isa ii compatible dc/dc converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 manufacturer contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 appendix b: layout recommendations for reducing noise. . . . . . . . . . . . . . . . . . . . . . . .174 decoupling low-pass r/c filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 digital decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 analog decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 avss1 and avdd3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 avss2 and avdd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 avss2 and avdd2/avdd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 appendix c: sample plug and play configuration record . . . . . . . . . . . . . . . . . . . . . . . .176 sample configuration file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 appendix d: alternative method for initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
AM79C961A 9 preliminary appendix e: introduction of the look ahead packet processing (lapp) concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 outline of the lapp flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 setup: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 lapp enable software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 lapp enable rules for parsing of descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 some examples of lapp descriptor interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 buffer size tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 appendix f: some characteristics of the xxc56 serial eeprom . . . . . . . . . . . . . . . . . . .188 switching characteristics of a typical xxc56 serial eeprom interface . . . . . . . . . . .188 instruction set for the xxc56 series of eeproms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
10 AM79C961A preliminary block diagram: bus master mode 19364a-1 isa bus interface unit rcv fifo xmt fifo fifo control buffer management unit eeprom interface unit 802.3 mac core encoder/ decoder (pls) & aui port 10base-t mau private bus control jtag port control aen dack [3, 5?] drq[3, 5?] iochrdy iocs16 ior io w irq[3, 4, 5, 9, 10, 11, 12] master memr memw ref reset sbhe bale sd[0-15] la[17-23] sa[0-19] sleep shfbusy eedo eedi eesk eecs dvdd[1-7] dvss[1-13] avdd[1-4] avss[1-2] dxcvr/ear ci+/ di+/ xtal1 xtal2 do+/ rxd+/ txd+/ txpd+/ irq15/apcs bpcs led [0?] prdb[0?] tdo tms tdi tck
AM79C961A 11 preliminary connection diagrams: bus master mode 132 1 dvdd2 tck 131 tms 130 tdo 129 tdi 128 eecs 127 bpcs 126 shfbusy 125 prdb0/eesk 124 prdb1/eedi 123 prdb2/eedo 122 prdb3 121 dvss2 120 prdb4 119 prdb5 118 prdb6 117 prdb7 116 dvdd1 115 led0 114 led1 113 dvss1 112 led2 111 led3 110 dxcvr/ ear 109 avdd2 108 ci+ 107 ci 106 di+ 105 di 104 avdd1 103 do+ 102 do 101 avss1 100 xtal2 99 avss2 98 xtal1 97 avdd3 96 txd+ 95 txpd+ 94 txd 93 txpd 92 avdd4 91 rxd+ 90 rxd 89 dvss13 88 sd15 87 sd7 86 sd14 85 sd6 84 dvss9 83 sd13 82 sd5 81 sd12 80 sd4 79 dvdd7 78 sd11 77 sd3 76 sd10 75 sd2 74 dvss8 73 sd9 72 sd1 71 sd8 70 sd0 69 sleep 68 dvdd6 67 34 dvdd4 35 sa12 36 sa13 37 sa14 38 sa15 39 sa16 40 sa17 41 sa18 42 sa19 43 aen 44 iochrdy 45 memw 46 memr 47 dvss11 48 irq15/ apcs 49 irq12/ flashwe 50 irq11 51 dvdd5 52 irq10 53 iocs16 54 bale 55 irq3 56 irq4 57 irq5 58 59 dvss12 60 drq3 61 dack3 62 ior 63 iow 64 irq9 65 reset 66 dvss3 2 master 3 drq7 4 drq6 5 drq5 6 dvss10 7 dack7 8 dack6 9 dack5 10 la17 11 la18 12 la19 13 la20 14 dvss4 15 la21 16 la22 17 la23 18 sbhe 19 dvdd3 20 sa0 21 sa1 22 sa2 23 dvss5 24 sa3 25 sa4 26 sa5 27 sa6 28 sa7 29 sa8 30 sa9 31 dvss6 32 sa10 33 sa11 top side view ref dvss7 19364a-2
12 AM79C961A preliminary pin designations: bus master mode listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 dvss3 34 dvdd4 67 dvdd6 100 avss1 2 master 35 sa12 68 sleep 101 do 3 drq7 36 sa13 69 sd0 102 do+ 4 drq6 37 sa14 70 sd8 103 avdd1 5 drq5 38 sa15 71 sd1 104 di 6 dvss10 39 dvss7 72 sd9 105 di+ 7d a ck7 40 sa16 73 dvss8 106 ci 8d a ck6 41 sa17 74 sd2 107 ci+ 9d a ck5 42 sa18 75 sd10 108 avdd2 10 la17 43 sa19 76 sd3 109 dxcvr/ear 11 la18 44 aen 77 sd11 110 led3 12 la19 45 iochrdy 78 dvdd7 111 led2 13 la20 46 memw 79 sd4 112 dvss1 14 dvss4 47 memr 80 sd12 113 led1 15 la21 48 dvss11 81 sd5 114 led0 16 la22 49 irq15/apcs 82 sd13 115 dvdd1 17 la23 50 irq12/flashwe 83 dvss9 116 prdb7 18 sbhe 51 irq11 84 sd6 117 prdb6 19 dvdd3 52 dvdd5 85 sd14 118 prdb5 20 sa0 53 irq10 86 sd7 119 prdb4 21 sa1 54 iocs16 87 sd15 120 dvss2 22 sa2 55 bale 88 dvss13 121 prdb3 23 dvss5 56 irq3 89 rxd 122 prdb2/eedo 24 sa3 57 irq4 90 rxd+ 123 prdb1/eedi 25 sa4 58 irq5 91 avdd4 124 prdb0/eesk 26 sa5 59 ref 92 txpd 125 shfbusy 27 sa6 60 dvss12 93 txd 126 bpcs 28 sa7 61 drq3 94 txpd+ 127 eecs 29 sa8 62 d a ck3 95 txd+ 128 tdi 30 sa9 63 ior 96 avdd3 129 tdo 31 dvss6 64 io w 97 xtal1 130 tms 32 sa10 65 irq9 98 avss2 131 tck 33 sa11 66 reset 99 xtal2 132 dvdd2
AM79C961A 13 preliminary pin designations: bus master mode listed by pin number pin name pin no. pin name pin no. pin name pin no. pin name pin no. aen 44 dvss12 60 led2 111 sa6 27 avdd1 103 dvss13 88 led3 110 sa7 28 avdd2 108 dvss2 120 master 2 sa8 29 avdd3 96 dvss3 1 memr 47 sa9 30 avdd4 91 dvss4 14 memw 46 sbhe 18 avss1 100 dvss5 23 prdb0/eesk 124 sd0 69 avss2 98 dvss6 31 prdb1/eedi 123 sd1 71 bale 55 dvss7 39 prdb2/eedo 122 sd10 75 bpcs 126 dvss8 73 prdb3 121 sd11 77 ci 106 dvss9 83 prdb4 119 sd12 80 ci+ 107 dxcvr/ear 109 prdb5 118 sd13 82 d a ck3 62 eecs 127 prdb6 117 sd14 85 d a ck5 9 iochrdy 45 prdb7 116 sd15 87 d a ck6 8 iocs16 54 ref 59 sd2 74 d a ck7 7 ior 63 reset 66 sd3 76 di 104 io w 64 rxd 89 sd4 79 di+ 105 irq10 53 rxd+ 90 sd5 81 do 101 irq11 51 sa0 20 sd6 84 do+ 102 irq12/flashwe 50 sa1 21 sd7 86 drq3 61 irq15/apcs 49 sa10 32 sd8 70 drq5 5 irq3 56 sa11 33 sd9 72 drq6 4 irq4 57 sa12 35 shfbusy 125 drq7 3 irq5 58 sa13 36 sleep 68 dvdd1 115 irq9 65 sa14 37 tck 131 dvdd2 132 la17 10 sa15 38 tdi 128 dvdd3 19 la18 11 sa16 40 tdo 129 dvdd4 34 la19 12 sa17 41 tms 130 dvdd5 52 la20 13 sa18 42 txd 93 dvdd6 67 la21 15 sa19 43 txd+ 95 dvdd7 78 la22 16 sa2 22 txpd 92 dvss1 112 la23 17 sa3 24 txpd+ 94 dvss10 6 led0 114 sa4 25 xtal1 97 dvss11 48 led1 113 sa5 26 xtal2 99
14 AM79C961A preliminary pin designations: bus master mode listed by group pin name pin function i/o driver isa bus interface aen bale d a ck [3, 5?] drq[3, 5?] iochrdy iocs16 ior io w irq[3, 4, 5, 9, 10, 11, 12, 15] la[17-23] master memr memw ref reset sa[0 ?9] sbhe sd[0 ?5] address enable bus address latch enable dma acknowledge dma request i/o channel ready i/o chip select 16 i/o read select i/o write select interrupt request unlatched address bus master transfer in progress memory read select memory write select memory refresh active system reset system address bus system byte high enable system data bus i i i i/o i/o o i i o i/o o o o i i i/o i/o i/o ts3 od3 od3 ts3/od3 ts3 od3 ts3 ts3 ts3 ts3 ts3 board interfaces irq15/apcs bpcs dxcvr/ear led0 led1 led2 led3 prdb[3?] sleep xtal1 xtal2 shfbusy prdb(0)/eesk prdb(1)/eedi prdb(2)/eedo eecs irq15 or address prom chip select boot prom chip select disable transceiver led0/lnkst led1 /sfbd/rcv a ct led2 /srd/rxd a tpol led3 /srdclk/xmt a ct prom data bus sleep mode crystal input crystal output read access from eeprom in process serial shift clock serial shift data in serial shift data out eeprom chip select o o i/o o o o o i/o i i o i/o i/o i/o o ts1 ts1 ts1 ts2 ts2 ts2 ts2 ts1
AM79C961A 15 preliminary pin designations: bus master mode (continued) listed by group output driver types pin name pin function i/o driver attachment unit interface (aui) ci di do collision inputs receive data transmit data i i o twisted pair transceiver interface (10base-t) rxd txd txpd 10base-t receive data 10base-t transmit data 10base-t predistortion control i o o ieee 1149.1 test access port interface (jtag) tck tdi tdo tms test clock test data input test data output test mode select i i o i ts2 power supplies avdd avss dvdd dvss analog power [1-4] analog ground [1-2] digital power [1-7] digital ground [1-13] name type iol (ma) ioh (ma) pf ts1 tri-state 4 1 50 ts2 tri-state 12 ? 50 ts3 tri-state 24 ? 120 od3 open drain 24 ? 120
16 AM79C961A preliminary pin description: bus master mode these pins are part of the bus master mode. in order to understand the pin descriptions, de?ition of some terms from a draft of ieee p996 are included. ieee p996 terminology alternate master : any device that can take control of the bus through assertion of the master signal. it has the ability to generate addresses and bus control sig- nals in order to perform bus operations. all alternate masters must be 16 bit devices and drive sbhe . bus ownership : the current master possesses bus ownership and can assert any bus control, address and data lines. current master : the permanent master, temporary master or alternate master which currently has owner- ship of the bus. permanent master : each p996 bus will have a device known as the permanent master that provides certain signals and bus control functions as described in sec- tion 3.5 (of the ieee p996 spec.), ?ermanent master? the permanent master function can reside on a bus adapter or on the backplane itself. temporary master : a device that is capable of gener- ating a dma request to obtain control of the bus and directly asserting only the memory and i/o strobes during bus transfer. addresses are generated by the dma device on the permanent master. isa interface aen address enable input this signal must be driven low when the bus performs an i/o access to the device. bale used to latch the la20?3 address lines. d a ck 3, 5-7 dma acknowledge input asserted low when the permanent master acknowl- edges a dma request. when d a ck is asserted the pcnet-isa ii controller becomes the current master by asserting the master signal. drq 3, 5-7 dma request input/output when the pcnet-isa ii controller needs to perform a dma transfer, it asserts drq. the permanent master acknowledges drq with the assertion of d a ck . when the pcnet-isa ii does not need the bus it desserts drq. the pcnet-isa ii provides for fair bus bandwidth sharing between two bus mastering devices on the isa bus through an adaptive delay which is inserted between back-to-back dma requests. see the back-to-back dma requests section for details. because of the operation of the plug and play regis- ters, the dma channels on the pcnet-isa ii must be attached to the speci? drq and dack signals on the pc/at bus as indicated by the pin names. iochrdy i/o channel ready input/output when the pcnet-isa ii controller is being accessed, iochrdy high indicates that valid data exists on the data bus for reads and that data has been latched for writes. when the pcnet-isa ii controller is the current master on the isa bus, it extends the bus cycle as long as iochrdy is low. iocs16 i/o chip select 16 output when an i/o read or write operation is performed, the pcnet-isa ii controller will drive the iocs16 pin low to indicate that the chip supports a 16-bit operation at this address. (if the motherboard does not receive this signal, then the motherboard will convert a 16-bit access to two 8-bit accesses). the pcnet-isa ii controller follows the ieee p996 spec- i?ation that recommends this function be implemented as a pure decode of sa0-9 and aen, with no depen- dency on ior , or io w ; however, some pc/at clone sys- tems are not compatible with this approach. for this reason, the pcnet-isa ii controller is recommended to be congured to run 8-bit i/o on all machines. since data is moved by memory cycles there is virtually no per- formance loss incurred by running 8-bit i/o and compat- ibility problems are virtually eliminated. the pcnet-isa ii controller can be congured to run 8-bit-only i/o by clearing bit 0 in plug and play register f0. ior i/o read input ior is driven low by the host to indicate that an input/ output read operation is taking place. ior is only valid if the aen signal is low and the external address matches the pcnet-isa ii controllers prede?ed i/o address location. if valid, ior indicates that a slave read operation is to be performed. io w i/o write input io w is driven low by the host to indicate that an input/ output write operation is taking place. io w is only valid if aen signal is low and the external address matches the pcnet-isa ii controllers prede?ed i/o address location. if valid, io w indicates that a slave write oper- ation is to be performed.
AM79C961A 17 preliminary irq 3, 4, 5, 9, 10, 11, 12, 15 interrupt request output an attention signal which indicates that one or more of the following status ?gs is set: babl, miss, merr, rint, idon, rcvcco, jab, mpco, or txdatstrt. all status ?gs have a mask bit which allows for sup- pression of irq assertion. these ?gs have the following meaning: because of the operation of the plug and play regis- ters, the interrupts on the pcnet-isa ii must be attached to speci? irq signals on the pc/at bus. la17-23 unlatched address bus input/output the unlatched address bus is driven by the pcnet-isa ii controller during bus master cycle. the functions of these unlatched address pins will change when gpsi mode is invoked. the following table shows the pin con?uration in gpsi mode. please refer to the section on general purpose serial interface for detailed information on accessing this mode. master master mode input/output this signal indicates that the pcnet-isa ii controller has become the current master of the isa bus. after the pcnet-isa ii controller has received a dma acknowledge (d a ck ) in response to a dma request (drq), the ethernet controller asserts the master signal to indicate to the permanent master that the pcnet-isa ii controller is becoming the current master. memr memory read input/output memr goes low to perform a memory read operation. memw memory write input/output memw goes low to perform a memory write operation. ref memory refresh input when ref is asserted, a memory refresh is active. the pcnet-isa ii controller uses this signal to mask inad- vertent dma acknowledge assertion during memory refresh periods. if d a ck is asserted when ref is active, d a ck assertion is ignored. ref is monitored to eliminate a bus arbitration problem observed on some isa platforms. reset reset input when reset is asserted high the pcnet-isa ii con- troller performs an internal system reset. reset must be held for a minimum of 10 xtal1 periods before being deasserted. while in a reset state, the pcnet-isa ii controller will tristate or deassert all outputs to pre- de?ed reset levels. the pcnet-isa ii controller resets itself upon power-up. sa0-19 system address bus input/output this bus contains address information, which is stable during a bus operation, regardless of the source. sa17-19 contain the same values as the unlatched address la17-19. when the pcnet-isa ii controller is the current master, sa0-19 will be driven actively. when the pcnet-isa ii controller is not the current master, the sa0-19 lines are continuously monitored to determine if an address match exists for i/o slave transfers or boot prom accesses. sbhe system byte high enable input/output this signal indicates the high byte of the system data bus is to be used. sbhe is driven by the pcnet-isa ii controller when performing bus mastering operations. sd0-15 system data bus input/output these pins are used to transfer data to and from the pcnet-isa ii controller to system resources via the isa data bus. sd0-15 is driven by the pcnet-isa ii control- babl babble rcvcco receive collision count over?w jab jabber miss missed frame merr memory error mpco missed packet count over?w rint receive interrupt idon initialization done txdatstrt transmit start pin number pin function in bus master mode pin function in gpsi mode 10 la17 rxdat 11 la18 srdclk 12 la19 rxcrs 13 la20 clsn 15 la21 stdclk 16 la22 txen 17 la23 txdat
18 AM79C961A preliminary ler when performing bus master writes and slave read operations. likewise, the data on sd0-15 is latched by the pcnet-isa ii controller when performing bus master reads and slave write operations. board interface irq12/flashwe flash write enable output optional interface to the flash memory boot prom write enable. irq15/apcs address prom chip select output when programmed as apcs in plug and play register f0, this signal is asserted when the external address prom is read. when an i/o read operation is performed on the ?st 16 bytes in the pcnet-isa ii con- trollers i/o space, apcs is asserted. the outputs of the external address prom drive the prom data bus. the pcnet-isa ii controller buffers the contents of the prom data bus and drives them on the lower eight bits of the system data bus. when programmed to irq15 (default), this pin has the same function as irq 3, 4, 5, 9, 10, 11, or 12. bpcs boot prom chip select output this signal is asserted when the boot prom is read. if sa0-19 lines match a prede?ed address block and memr is active and ref inactive, the bpcs signal will be asserted. the outputs of the external boot prom drive the prom data bus. the pcnet-isa ii controller buffers the contents of the prom data bus and drives them on the lower eight bits of the system data bus. dxcvr/ear disable transceiver/ external address reject input/output this pin can be used to disable external transceiver circuitry attached to the aui interface when the internal 10base-t port is active. the polarity of this pin is set by the dxcvrp bit (pnp register 0xf0, bit 5). when dxcvrp is cleared (default), the dxcvr pin is driven high when the twisted pair port is active or sleep mode has been entered and driven low when the aui port is active. when dxcvrp is set, the dxcvr pin is driven low when the twisted pair port is active or sleep mode has been entered and driven high when the aui port is active. if eadi mode is selected, this pin becomes the ear input. the incoming frame will be checked against the inter- nally active address detection mechanisms and the result of this check will be ord with the value on the ear pin. the ear pin is de?ed as reject . (see the eadi section for details regarding the function and timing of this signal). ledo-3 led drivers output these pins sink 12 ma each for driving leds. their meaning is software con?urable (see section the isa bus con?uration registers ) and they are active low. when eadi mode is selected, the pins named led1 , led2 , and led3 change in function while led0 continues to indicate 10base-t link status. prdb3-7 private data bus input/output this is the data bus for the boot prom and the address prom. prdb2/eedo private data bus bit 2/data out input/output a multifunction pin which serves as prdb2 of the private data bus and, when isacsr3 bit 4 is set, changes to become data out from the eeprom. prdb1/eedi private data bus bit 1/data in input/output a multifunction pin which serves as prdb1 of the private data bus and, when isacsr3 bit 4 is set, changes to become data in to the eeprom. prdb0/eesk private data bus bit 0/ serial clock input/output a multifunction pin which serves as prdb0 of the private data bus and, when isacsr3 bit 4 is set, changes to become serial clock to the eeprom. led eadi function 1 sf/bd 2 srd 3 srdclk
AM79C961A 19 preliminary shfbusy shift busy input/output this pin indicates that a read from the external eeprom is in progress. it is active only when data is being shifted out of the eeprom due to a hardware reset or assertion of the ee_load bit (isacsr3, bit 14). if this pin is left unconnected or pulled low with a pull-down resistor, an eeprom checksum error is forced. normally, this pin should be connected to v cc through a 10k w pull-up resistor. eecs eeprom chip select output this signal is asserted when read or write accesses are being performed to the eeprom. it is controlled by isacsr3. it is driven at reset during eeprom read. sleep sleep input when sleep pin is asserted (active low), the pcnet-isa ii controller performs an internal system reset and proceeds into a power savings mode. all outputs will be placed in their normal reset condition. all pcnet-isa ii controller inputs will be ignored except for the sleep pin itself. deassertion of sleep results in the device waking up. the system must delay the starting of the network controller by 0.5 seconds to allow internal analog circuits to stabilize. xtal1 crystal connection input the internal clock generator uses a 20 mhz crystal that is attached to pins xtal1 and xtal2. alternatively, an external 20 mhz cmos-compatible clock signal can be used to drive this pin. refer to the section on external crystal characteristics for more details. xtal2 crystal connection output the internal clock generator uses a 20 mhz crystal that is attached to pins xtal1 and xtal2. if an external clock is used, this pin should be left unconnected.
20 AM79C961A preliminary plug and play isa card state transitions notes: 1. csn = card select number. 2. reset_drv causes a state transition from the current state to wait for key and sets all csns to zero. all logical devices are set to their power-up con?uration values. 3. the wait for key command causes a state transition from the current state to wait for key. power up reset_drv state active commands initiation key set csn = 0 wait for key no active commands state active commands sleep reset wait for key wake[csn] state active commands isolation reset wait for key set rd_data port serial isolation wake[csn] state active commands con? reset wait for key wake[csn] resource data status logical device i/o range check activate con?uration registers set csn lose serial location or (wake <> csn) wake <> csn
AM79C961A 21 preliminary block diagram: bus slave mode 19364a-3 led [0-3] isa bus interface unit rcv fifo xmt fifo fifo control buffer management unit eeprom interface unit 802.3 mac core encoder/ decoder (pls) & aui port 10base-t mau private bus control jtag port control aen iochrdy ior io w irq[3, 4, 5, 9, 10, 11, 12] iocs16 memr memw ref reset sbhe sd[0-15] sa[0-15] sleep shfbusy eedo eedi eesk eecs dxcvr/ear ci+/- di+/- xtal1 xtal2 do+/- rxd+/- txd+/- txpd+/- tdo tms tdi tck sma irq15/apcs bpcs prab[0-15] prdb[0-7] sr oe sr we smam bp am dvdd[1-7] dvss[1-13] avdd[1-4] avss[1-2]
22 AM79C961A preliminary connection diagrams: bus slave mode 19364a-4 132 1 dvdd2 tck 131 tms 130 tdo 129 tdi 128 eecs 127 bpcs 126 shfbusy 125 prdb0/eesk 124 prdb1/eedi 123 prdb2/eedo 122 prdb3 121 dvss2 120 prdb4 119 prdb5 118 prdb6 117 prdb7 116 dvdd1 115 led0 114 led1 113 dvss1 112 led2 111 led3 110 dxcvr/ ear 109 avdd2 108 ci+ 107 ci 106 di+ 105 di 104 av dd1 103 do+ 102 do 101 avss1 100 xtal2 99 avss2 98 xtal1 97 avdd3 96 txd+ 95 txpd+ 94 txd 93 txpd 92 avdd4 91 rxd+ 90 rxd 89 dvss13 88 sd15 87 sd7 86 sd14 85 sd6 84 dvss9 83 sd13 82 sd5 81 sd12 80 sd4 79 dvdd7 78 sd11 77 sd3 76 sd10 75 sd2 74 dvss8 73 sd9 72 sd1 71 sd8 70 sd0 69 sleep 68 dvdd6 67 34 dvdd4 35 prab12 36 prab13 37 prab14 38 prab15 39 sa13 40 sa14 41 sa15 42 srwe 43 aen 44 iochrdy 45 memw 46 memr 47 dvss11 48 apcs /irq15 49 srcs /irq12 50 irq11 51 dvdd5 52 irq10 53 iocs16 54 bpam 55 irq3 56 irq4 57 irq5 58 59 dvss12 60 sroe 61 smam 62 ior 63 iow 64 irq9 65 reset 66 dvss3 2 sma 3 sa0 4 sa1 5 sa2 6 dvss10 7 sa3 8 sa4 9 sa5 10 sa6 11 sa7 12 sa8 13 sa9 14 dvss4 15 sa10 16 sa11 17 sa12 18 sbhe 19 dvdd3 20 prab0 21 prab1 22 prab2 23 dvss5 24 prab3 25 prab4 26 prab5 27 prab6 28 prab7 29 prab8 30 prab9 31 dvss6 32 prab10 33 prab11 top side view ref dvss7
AM79C961A 23 preliminary pin designations: bus slave mode listed by pin number pin # name pin # name pin # name 1 dvss3 sma sa0 sa1 sa2 dvss10 sa3 sa4 sa5 sa6 sa7 sa8 45 iochrdy 89 rxd- rxd+ avdd4 txpd- txd- txpd+ txd+ avdd3 xtal1 avss2 xtal2 avss1 do- do+ avdd1 di- di+ ci- ci+ avdd2 dxcvr/ear led3 led2 dvss1 led1 led0 2 46 memw 90 3 47 memr 91 4 48 dvss11 92 5 49 irq15 93 6 50 irq12 94 7 51 irq11 95 8 52 dvdd5 96 9 53 irq10 97 10 54 iocs16 98 11 55 bp am 99 12 56 irq3 100 13 sa9 dvss4 sa10 sa11 sa12 sbhe dvdd3 prab0 prab1 prab2 dvss5 prab3 prab4 prab5 prab6 prab7 prab8 prab9 dvss6 prab10 prab11 dvdd4 prab12 prab13 57 irq4 101 14 58 irq5 102 15 59 ref 103 16 60 dvss12 104 17 61 sr oe 105 18 62 smam 106 19 63 ior 107 20 64 io w 108 21 65 irq9 109 22 66 reset 110 23 67 dvdd6 111 24 68 sleep 112 25 69 sd0 113 26 70 sd8 114 27 71 sd1 115 dvdd1 prdb7 prdb6 prdb5 prdb4 dvss2 prdb3 prdb2/eedo prdb1/eedi prdb0/eesk shfbusy bpcs eecs tdi tdo tms tck dvdd2 28 72 sd9 116 29 73 dvss8 117 30 74 sd2 118 31 75 sd10 119 32 76 sd3 120 33 77 sd11 121 34 78 dvdd7 122 35 79 sd4 123 36 80 sd12 124 37 prab14 prab15 dvss7 sa13 sa14 sa15 sr we aen 81 sd5 125 38 82 sd13 126 39 83 dvss9 127 40 84 sd6 128 41 85 sd14 129 42 86 sd7 130 43 87 sd15 131 44 88 dvss13 132
24 AM79C961A preliminary pin designations: bus slave mode listed by pin name name pin# name pin# name pin# aen avdd1 avdd2 avdd3 avdd4 avss1 avss2 bp am bpcs ci- ci+ di- di+ do- do+ dvdd1 dvdd2 dvdd3 dvdd4 dvdd5 dvdd6 dvdd7 dvss1 dvss10 dvss11 dvss12 44 irq15 49 sa13 sa14 sa15 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sbhe sd0 sd1 sd10 sd11 sd12 sd13 sd14 sd15 sd2 sd3 sd4 40 103 irq3 56 41 108 irq4 57 42 96 irq5 58 5 91 irq9 65 7 100 led0 114 8 98 led1 113 9 55 led2 111 10 126 led3 110 11 106 memr 47 12 107 memw 46 13 104 prab0 20 18 105 prab1 21 69 101 prab10 32 71 102 prab11 33 75 115 prab12 35 77 132 prab13 36 80 19 prab14 37 82 34 prab15 38 85 52 prab2 22 87 67 prab3 24 74 78 prab4 25 76 112 prab5 26 79 6 prab6 27 sd5 sd6 sd7 sd8 sd9 shfbusy sleep sma smam sr oe sr we tck tdi tdo tms txd- txd+ txpd- txpd+ xtal1 xtal2 81 48 prab7 28 84 60 prab8 29 86 dvss13 dvss2 dvss3 dvss4 dvss5 dvss6 dvss7 dvss8 dvss9 dxcvr/ear eecs iochrdy iocs16 ior io w irq10 irq11 irq12 88 prab9 30 70 120 prdb0/do 124 72 1 prdb0/d1 123 125 14 prdb0/sclk 122 68 23 prdb3 121 2 31 prdb4 119 62 39 prdb5 118 61 73 prdb6 117 43 83 prdb7 116 131 109 ref 59 128 127 reset 66 129 45 rxd- 89 130 54 rxd+ 90 93 63 sa0 3 95 64 sa1 4 92 53 sa10 15 94 51 sa11 16 97 50 sa12 17 99
AM79C961A 25 preliminary pin designations: bus slave mode listed by group pin name pin function i/o driver isa bus interface aen address enable i iochrdy i/o channel ready o od3 iocs16 i/o chip select 16 o od3 ior i/o read select i io w i/o write select i irq[3, 4, 5, 9, 10, 11, 12, 15] interrupt request o ts3/od3 memr memory read select i memw memory write select i ref memory refresh active i reset system reset i sa[0?5] system address bus i sbhe system byte high enable i sd[0?5] system data bus i/o ts3 board interfaces irq15/apcs irq15 or address prom chip select o ts1 bpcs boot prom chip select o ts1 bp am boot prom address match i dxcvr/ear disable transceiver i/o ts1 led0 led0 /lnkst o ts2 led1 led1 /sfbd /rcv a ct o ts2 led2 led2 /srd /rxd a td01 o ts2 led3 led3 /srdclk /xmt a ct o ts2 prab[0?5] private address bus i/o ts3 prdb[3?] private data bus i/o ts1 sleep sleep mode i sma slave mode architecture i smam shared memory address match i sr oe static ram output enable o ts3 sr we static ram write enable o ts1 xtal1 crystal oscillator input i xtal2 crystal oscillator output o shfbusy read access from eeprom in process o prdb(0)/eesk serial shift clock i/o prdb(1)/eedi serial shift data in i/o prdb(2)/eedo serial shift data out i/o eecs eeprom chip select o
26 AM79C961A preliminary pin designations: bus slave mode listed by group output driver types pin name pin function i/o driver attachment unit interface (aui) ci di do collision inputs receive data transmit data i i o twisted pair transceiver interface (10base-t) rxd txd txpd 10base-t receive data 10base-t transmit data 10base-t predistortion control i o o ieee 1149.1 test access port interface (jtag) tck tdi tdo tms test clock test data input test data output test mode select i i o i ts2 power supplies avdd avss dvdd dvss analog power [1-4] analog ground [1-2] digital power [1-7] digital ground [1-13] name type i ol (ma) i oh (ma) pf ts1 tri-state 4 1 50 ts2 tri-state 12 ? 50 ts3 tri-state 24 ? 120 od3 open drain 24 ? 120
AM79C961A 27 preliminary pin description: bus slave mode isa interface aen address enable input this signal must be driven low when the bus performs an i/o access to the device. iochrdy i/o channel ready output when the pcnet-isa ii controller is being accessed, a high on iochrdy indicates that valid data exists on the data bus for reads and that data has been latched for writes. iocs16 i/o chip select 16 input/output when an i/o read or write operation is performed, the pcnet-isa ii controller will drive this pin low to indi- cate that the chip supports a 16-bit operation at this address. (if the motherboard does not receive this signal, then the motherboard will convert a 16-bit access to two 8-bit accesses). the pcnet-isa ii controller follows the ieee p996 spec- i?ation that recommends this function be implemented as a pure decode of sa0-9 and aen, with no depen- dency on ior , or io w ; however, some pc/at clone systems are not compatible with this approach. for this reason, the pcnet-isa ii controller is recommended to be congured to run 8-bit i/o on all machines. since data is moved by memory cycles there is virtually no performance loss incurred by running 8-bit i/o and compatibility problems are virtually eliminated. the pcnet-isa ii controller can be con?ured to run 8-bit-only i/o by clearing bit 0 in plug and play register f0. ior i/o read input to perform an input/output read operation on the device ior must be asserted. ior is only valid if the aen signal is low and the external address matches the pcnet-isa ii controllers prede?ed i/o address location. if valid, ior indicates that a slave read opera- tion is to be performed. io w i/o write input to perform an input/output write operation on the device io w must be asserted. io w is only valid if aen signal is low and the external address matches the pcnet-isa ii controllers prede?ed i/o address loca- tion. if valid, io w indicates that a slave write operation is to be performed. irq3, 4, 5, 9, 10, 11, 12, 15 interrupt request output an attention signal which indicates that one or more of the following status ?gs is set: babl, miss, merr, rint, idon or txstrt. all status ?gs have a mask bit which allows for suppression of irq assertion. these ?gs have the following meaning: memr memory read input memr goes low to perform a memory read operation. memw memory write input memw goes low to perform a memory write opera- tion. ref memory refresh input when ref is asserted, a memory refresh cycle is in progress. during a refresh cycle, memr assertion is ignored. reset reset input when reset is asserted high, the pcnet-isa ii controller performs an internal system reset. reset must be held for a minimum of 10 xtal1 periods before being deasserted. while in a reset state, the pcnet-isa ii controller will tristate or deassert all outputs to predened reset levels. the pcnet-isa ii controller resets itself upon power-up. sa0-15 system address bus input this bus carries the address inputs from the system address bus. address data is stable during command active cycle. babl babble rcvcco receive collision count over?w jab jabber miss missed frame merr memory error mpco missed packet count over?w rint receive interrupt idon initialization done txstrt transmit start
28 AM79C961A preliminary sbhe system bus high enable input this signal indicates the high byte of the system data bus is to be used. there is a weak pull-up resistor on this pin. if the pcnet-isa ii controller is installed in an 8-bit only system like the pc/xt, sbhe will always be high and the pcnet-isa ii controller will perform only 8-bit operations. there must be at least one low going edge on this signal before the pcnet-isa ii controller will perform 16-bit operations. sd0-15 system data bus input/output this bus is used to transfer data to and from the pcnet-isa ii controller to system resources via the isa data bus. sd0-15 is driven by the pcnet-isa ii controller when performing slave read operations. likewise, the data on sd0-15 is latched by the pcnet-isa ii controller when performing slave write operations. board interface apcs /irq15 address prom chip select output this signal is asserted when the external address prom is read. when an i/o read operation is per- formed on the ?st 16 bytes in the pcnet-isa ii controllers i/o space, apcs is asserted. the outputs of the external address prom drive the prom data bus. the pcnet-isa ii controller buffers the contents of the prom data bus and drives them on the lower eight bits of the system data bus. iocs16 is not asserted during this cycle. bp am boot prom address match input this pin indicates a boot prom access cycle. if no boot prom is installed, this pin has a default value of high and thus may be left connected to v dd . bpcs boot prom chip select output this signal is asserted when the boot prom is read. if bp am is active and memr is active, the bpcs signal will be asserted. the outputs of the external boot prom drive the prom data bus. the pcnet-isa ii controller buffers the contents of the prom data bus and drives them on the system data bus. iocs16 is not asserted during this cycle. if 16-bit cycles are performed, it is the responsibility of external logic to assert memcs16 signal. dxcvr/ear disable transceiver/ external address reject input/output this pin disables the transceiver. the dxcvr output is congured in the initialization sequence. a high level indicates the twisted pair interface is active and the aui is inactive, or sleep mode has been entered. a low level indicates the aui is active and the twisted pair interface is inactive. if eadi mode is selected, this pin becomes the ear input. the incoming frame will be checked against the inter- nally active address detection mechanisms and the result of this check will be ord with the value on the ear pin. the ear pin is de?ed as reject . (see the eadi section for details regarding the function and tim- ing of this signal). led0-3 led drivers output these pins sink 12 ma each for driving leds. their meaning is software con?urable (see section the isa bus con?uration registers ) and they are active low. when eadi mode is selected, the pins named led1 , led2 , and led3 change in function while led0 continues to indicate 10base-t link status. the dxcvr input becomes the ear input. prab0-15 private address bus input/output the private address bus is the address bus used to drive the address prom, remote boot prom, and sram. prab10-15 are required to be buffered by a bus buffer with aboe as its control and sa10-15 as its inputs. prdb3-7 private data bus input/output this is the data bus for the static ram, the boot prom, and the address prom. prdb2/eedo private data bus bit 2/data out input/output a multifunction pin which serves as prdb2 of the private data bus and, when isacsr3 bit 4 is set, changes to become data out from the eeprom. led eadi function 1 sf/bd 2 srd 3 srdclk
AM79C961A 29 preliminary prdb1/eedi private data bus bit 1/data in input/output a multifunction pin which serves as prdb1 of the private data bus and, when isacsr3 bit 4 is set, changes to become data in to the eeprom. prdb0/eesk private data bus bit 0/ serial clock input/output a multifunction pin which serves as prdb0 of the private data bus and, when isacsr3 bit 4 is set, changes to become serial clock to the eeprom. shfbusy shift busy input/output this pin indicates that a read from the external eeprom is in progress. it is active only when data is being shifted out of the eeprom due to a hardware reset or assertion of the ee_load bit (isacsr3, bit 14). if this pin is left unconnected or pulled low with a pull-down resistor, an eeprom checksum error is forced. normally, this pin should be connected to v cc through a 10k w pull-up resistor. eecs eeprom chip select output this signal is asserted when read or write accesses are being performed to the eeprom. it is controlled by isacsr3. it is driven at reset during eeprom read. sleep sleep input when sleep input is asserted (active low), the pcnet-isa ii controller performs an internal system reset and proceeds into a power savings mode. all out- puts will be placed in their normal reset condition. all pcnet-isa ii controller inputs will be ignored except for the sleep pin itself. deassertion of sleep results in the device waking up. the system must delay the starting of the network controller by 0.5 seconds to allow internal analog circuits to stabilize. sma slave mode architecture input this pin must be permanently pulled low for operation in the bus slave mode. it is sampled after the hardware reset sequence. in the bus slave mode, the pcnet-isa ii can be programmed for shared memory access or programmed i/o access through the piosel bit (isacsr2, bit 13). smam shared memory address match input when the shared memory architecture is selected (isacsr2, bit 13), this pin is an input that indicates an access to shared memory when asserted. the type of access is decided by memr or memw . when the programmed i/o architecture is selected, this pin should be permanently tied high. sr oe static ram output enable output this pin directly controls the external srams oe pin. srcs /irq12 static ram chip select output this pin directly controls the external srams chip select (cs ) pin when the flash boot rom option is selected. when flash boot rom option is not selected, this pin becomes irq12. sr we/we static ram write enable/ write enable output this pin (sr we ) directly controls the external srams we pin when a flash memory device is not implemented. when a flash memory device is implemented, this pin becomes a global write enable (we ) pin. xtal1 crystal connection input the internal clock generator uses a 20 mhz crystal that is attached to pins xtal1 and xtal2. alternatively, an external 20 mhz cmos-compatible clock signal can be used to drive this pin. refer to the section on external crystal characteristics for more details. xtal2 crystal connection output the internal clock generator uses a 20 mhz crystal that is attached to pins xtal1 and xtal2. if an external clock is used, this pin should be left unconnected.
30 AM79C961A preliminary pin description: network interfaces aui ci+, ci control input input this is a differential input pair used to detect collision (signal quality error signal). di+, di data in input this is a differential receive data input pair to the pcnet-isa ii controller. do+, do data out output this is a differential transmit data output pair from the pcnet-isa ii controller. twisted pair interface rxd+, rxd receive data input this is the 10base-t port differential receive input pair. txd+, txd transmit data output these are the 10base-t port differential transmit drivers. txp+, txp transmit predistortion control output these are 10base-t transmit waveform pre-distortion control differential outputs. pin description: ieee 1149.1 (jtag) test access port tck test clock input this is the clock input for the boundary scan test mode operation. tck can operate up to 10 mhz. tck does not have an internal pull-up resistor and must be con- nected to a valid ttl level of high or low. tck must not be left unconnected. tdi test data input input this is the test data input path to the pcnet-isa ii con- troller. if left unconnected, this pin has a default value of high. tdo test data output output this is the test data output path from the pcnet-isa ii controller. tdo is tri-stated when jtag port is inactive. tms test mode select input this is a serial input bit stream used to de?e the spe- ci? boundary scan test to be executed. if left uncon- nected, this pin has a default value of high. pin description: power supplies all power pins with a ? pre? are digital pins con- nected to the digital circuitry and digital i/o buffers. all power pins with an ? pre? are analog power pins connected to the analog circuitry. not all analog pins are quiet and special precaution must be taken when doing board layout. some analog pins are more noisy than others and must be separated from the other analog pins. avdd1? analog power (4 pins) power supplies power to analog portions of the pcnet-isa ii controller. special attention should be paid to the printed circuit board layout to avoid excessive noise on these lines. avss1? analog ground (2 pins) power supplies ground reference to analog portions of pcnet-isa ii controller. special attention should be paid to the printed circuit board layout to avoid exces- sive noise on these lines. dvdd1? digital power (7 pins) power supplies power to digital portions of pcnet-isa ii con- troller. four pins are used by input/output buffer drivers and two are used by the internal digital circuitry. dvss1?3 digital ground (13 pins) power supplies ground reference to digital portions of pcnet-isa ii controller. ten pins are used by input/out- put buffer drivers and two are used by the internal digital circuitry.
AM79C961A 31 preliminary connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 tqfp 144 AM79C961Avc
32 AM79C961A preliminary pin designations: bus master mode (tqfp 144) listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 37 nc 73 nc 109 nc 2 dvss3 38 dvdd4 74 dvdd6 110 avss1 3 master 39 sa12 75 sleep 111 do 4 drq7 40 sa13 76 sd0 112 do+ 5 drq6 41 sa14 77 sd8 113 avdd1 6 drq5 42 sa15 78 sd1 114 di 7 dvss10 43 dvss7 79 sd9 115 di+ 8d a ck7 44 sa16 80 dvss8 116 ci 9d a ck6 45 sa17 81 sd2 117 ci+ 10 d a ck5 46 sa18 82 sd10 118 avdd2 11 la17 47 sa19 83 sd3 119 dxcvr/ear 12 la18 48 aen 84 sd11 120 led3 13 la19 49 iochrdy 85 dvdd7 121 led2 14 la20 50 memw 86 sd4 122 dvss1 15 dvss4 51 memr 87 sd12 123 led1 16 la21 52 dvss11 88 sd5 124 led0 17 sa22 53 irq15/apcs 89 sd13 125 dvdd1 18 sa23 54 irq12/flashwe 90 dvss9 126 prdb7 19 sbhe 55 irq11 91 sd6 127 prdb6 20 dvdd3 56 dvdd5 92 sd14 128 prdb5 21 sa0 57 irq10 93 sd7 129 prdb4 22 sa1 58 iocs16 94 sd15 130 dvss2 23 sa2 59 bale 95 dvss13 131 prdb3 24 dvss5 60 irq3 96 rxd 132 prdb2/eedo 25 sa3 61 irq4 97 rxd+ 133 prdb1/eedi 26 sa4 62 irq5 98 avdd4 134 prdb0/eesk 27 sa5 63 ref 99 txpd 135 shfbusy 28 sa6 64 dvss12 100 txd 136 bpcs 29 sa7 65 drq3 101 txpd+ 137 eecs 30 sa8 66 d a ck3 102 txd+ 138 tdi 31 sa9 67 ior 103 avdd3 139 tdo 32 dvss6 68 io w 104 xtal1 140 tms 33 sa10 69 irq9 105 avss2 141 tck 34 sa11 70 reset 106 xtal2 142 dvdd2 35 nc 71 nc 107 nc 143 nc 36 nc 72 nc 108 nc 144 nc
AM79C961A 33 preliminary pin designations: bus master mode (tqfp 144) listed by pin name pin name pin no. pin name pin no. pin name pin no. pin name pin no. aen 48 dvss3 2 nc 37 sa3 25 avdd1 113 dvss4 15 nc 71 sa4 26 avdd2 118 dvss5 24 nc 72 sa5 27 avdd3 103 dvss6 32 nc 73 sa6 28 avdd4 98 dvss7 43 nc 107 sa7 29 avss1 110 dvss8 80 nc 108 sa8 30 avss2 105 dvss9 90 nc 109 sa9 31 bale 59 dxcvr/ear 119 nc 143 sbhe 19 bpcs 136 eecs 137 nc 144 sd0 76 ci+ 117 iochrdy 49 prdb0/eesk 134 sd1 78 ci 116 iocs16 58 prdb1/eedi 133 sd10 82 dack3 66 ior 67 prdb2/eedo 132 sd11 84 dack5 10 io w 68 prdb3 131 sd12 87 dack6 9 irq10 57 prdb4 129 sd13 89 dack7 8 irq11 55 prdb5 128 sd14 92 di+ 115 irq12/flashwe 54 prdb6 127 sd15 94 di 114 irq15/apcs 53 prdb7 126 sd2 81 do+ 112 irq3 60 ref 63 sd3 83 do 111 irq4 61 reset 70 sd4 86 drq3 65 irq5 62 rxd+ 97 sd5 88 drq5 6 irq9 69 rxd 96 sd6 91 drq6 5 la17 11 sa0 21 sd7 93 drq7 4 la18 12 sa1 22 sd8 77 dvdd1 125 la19 13 sa10 33 sd9 79 dvdd2 142 la20 14 sa11 34 shfbusy 135 dvdd3 20 la21 16 sa12 39 sleep 75 dvdd4 38 led0 124 sa13 40 tck 141 dvdd5 56 led1 123 sa14 41 tdi 138 dvdd6 74 led2 121 sa15 42 tdo 139 dvdd7 85 led3 120 sa16 44 tms 140 dvss1 122 master 3 sa17 45 txd+ 102 dvss10 7 memr 51 sa18 46 txd 100 dvss11 52 memw 50 sa19 47 txpd+ 101 dvss12 64 nc 1 sa2 23 txpd 99 dvss13 95 nc 35 sa22 17 xtal1 104 dvss2 130 nc 36 sa23 18 xtal2 106
34 AM79C961A preliminary pin designations: bus slave (pio and shared memory) modes (tqfp 144) listed by pin number pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 37 nc 73 nc 109 nc 2 dvss3 38 dvdd4 74 dvdd6 110 avss1 3 sma 39 prab12 75 sleep 111 do- 4 sa0 40 prab13 76 sd0 112 do+ 5 sa1 41 prab14 77 sd8 113 avdd1 6 sa2 42 prab15 78 sd1 114 di- 7 dvss10 43 dvss7 79 sd9 115 di+ 8 sa3 44 sa13 80 dvss8 116 ci- 9 sa4 45 sa14 81 sd2 117 ci+ 10 sa5 46 sa15 82 sd10 118 avdd2 11 sa6 47 sr we 83 sd3 119 dxcvr/ear 12 sa7 48 aen 84 sd11 120 led3 13 sa8 49 iochrdy 85 dvdd7 121 led2 14 sa9 50 memw 86 sd4 122 dvss1 15 dvss4 51 memr 87 sd12 123 led1 16 sa10 52 dvss11 88 sd5 124 led0 17 sa11 53 irq15 89 sd13 125 dvdd1 18 sa12 54 irq12 90 dvss9 126 prdb7 19 sbhe 55 irq11 91 sd6 127 prdb6 20 dvdd3 56 dvdd5 92 sd14 128 prdb5 21 prab0 57 irq10 93 sd7 129 prdb4 22 prab1 58 iocs16 94 sd15 130 dvss2 23 prab2 59 bp am 95 dvss13 131 prdb3 24 dvss5 60 irq3 96 rxd- 132 prdb2/ eedo 25 prab3 61 irq4 97 rxd+ 133 prdb1/eedi 26 prab4 62 irq5 98 avdd4 134 prdb0/eesk 27 prab5 63 ref 99 txpd- 135 shfbusy 28 prab6 64 dvss12 100 txd- 136 bpcs 29 prab7 65 sr oe 101 txpd+ 137 eecs 30 prab8 66 smam 102 txd+ 138 tdi 31 prab9 67 ior 103 avdd3 139 tdo 32 dvss6 68 io w 104 xtal1 140 tms 33 prab10 69 irq9 105 avss2 141 tck 34 prab11 70 reset 106 xtal2 142 dvdd2 35 nc 71 pcmcia_mode 107 nc 143 nc 36 nc 72 nc 108 nc 144 nc
AM79C961A 35 preliminary pin designations: bus slave (pio and shared memory) modes (tqfp 144) listed by pin name pin name pin no. pin name pin no. pin name pin no. pin name pin no. aen 48 eecs 137 prab13 40 sa7 12 avdd1 113 iochrdy 49 prab14 41 sa8 13 avdd2 118 iocs16 58 prab15 42 sa9 14 avdd3 103 ior 67 prab2 23 sbhe 19 avdd4 98 iow 68 prab3 25 sd0 76 avss1 110 irq10 57 prab4 26 sd1 78 avss2 105 irq11 55 prab5 27 sd10 82 bpam 59 irq12 54 prab6 28 sd11 84 bpcs 136 irq15 53 prab7 29 sd12 87 ci+ 117 irq3 60 prab8 30 sd13 89 ci 116 irq4 61 prab9 31 sd14 92 di+ 115 irq5 62 prdb0/eesk 134 sd15 94 di 114 irq9 69 prdb1/eedi 133 sd2 81 do+ 112 led0 124 prdb2/eedo 132 sd3 83 do 111 led1 123 prdb3 131 sd4 86 dvdd1 125 led2 121 prdb4 129 sd5 88 dvdd2 142 led3 120 prdb5 128 sd6 91 dvdd3 20 memr 51 prdb6 127 sd7 93 dvdd4 38 memw 50 prdb7 126 sd8 77 dvdd5 56 nc 1 ref 63 sd9 79 dvdd6 74 nc 35 reset 70 shfbusy 135 dvdd7 85 nc 36 rxd+ 97 sleep 75 dvss1 122 nc 37 rxd 96 smam 66 dvss10 7 nc 72 sa0 4 sma 3 dvss11 52 nc 73 sa1 5 sr oe 65 dvss12 64 nc 107 sa10 16 sr we 47 dvss13 95 nc 108 sa11 17 tck 141 dvss2 130 nc 109 sa12 18 tdi 138 dvss3 2 nc 143 sa13 44 tdo 139 dvss4 15 nc 144 sa14 45 tms 140 dvss5 24 pcmcia_mode 71 sa15 46 txd+ 102 dvss6 32 prab0 21 sa2 6 txd 100 dvss7 43 prab1 22 sa3 8 txpd+ 101 dvss8 80 prab10 33 sa4 9 txpd 99 dvss9 90 prab11 34 sa5 10 xtal1 104 dxcvr/ ear 119 prab12 39 sa6 11 xtal2 106
36 AM79C961A preliminary functional description the pcnet-isa ii controller is a highly integrated system solution for the pc-at isa architecture. it provides a full duplex ethernet controller, aui port, and 10base-t transceiver. the pcnet-isa ii controller can be directly in- terfaced to an isa system bus. the pcnet-isa ii control- ler contains an isa bus interface unit, dma buffer management unit, 802.3 media access control function, separate 136-byte transmit and 128-byte receive fifos, ieee dened attachment unit interface (aui), and twisted-pair transceiver media attachment unit. in addi- tion, a sleep function has been incorporated which pro- vides low standby current for power sensitive applications. the pcnet-isa ii controller is register compatible with the lance (am7990) ethernet controller and pcnet-isa (am79c960). the dma buffer management unit supports the lance descriptor software model and the pcnet-isa ii controller is software compatible with the novell ne2100 and ne1500t add-in cards. external remote boot proms and ethernet physical address proms are supported. the location of the i/o registers, ethernet address prom, and the boot prom are determined by the programming of the registers in- ternal to pcnet-isa ii. these registers are loaded at reset from the eeprom, if an eeprom is utilized. normally, the ethernet physical address will be stored in the eeprom with the other con?uration data. this reduces the parts count, board space requirements, and power consumption. the option to use a standard parallel 8 bit prom is provided to manufactures who are concerned about the non-volatile nature of eeproms. the pcnet-isa ii controllers bus master architecture brings to system manufacturers (adapter card and motherboard makers alike) something they have not been able to enjoy with other architectures? low-cost system solution that provides the lowest parts count and highest performance. as a bus-mastering device, costly and power-hungry external srams are not needed for packet buffering. this results in lower sys- tem cost due to fewer components, less real-estate and less power. the pcnet-isa ii controllers advanced bus mastering architecture also provides high data through- put and low cpu utilization for even better performance. to offer greater ?xibility, the pcnet-isa ii controller has a bus slave mode to meet varying application needs. the bus slave mode utilizes a local sram memory to store the descriptors and buffers that are located in sys- tem memory when in bus master mode. the sram can be slave accessed on the isa bus through memory cycles in shared memory mode or i/o cycles in pro- grammed i/o mode. the shared memory and pro- grammed i/o architectures offer maximum compatibility with low-end machines, such as pc/xts that do not support bus mastering, and very high end machines which require local packet buffering for increased system latency. the network interface provides an attachment unit interface and twisted-pair transceiver functions. only one interface is active at any particular time. the aui allows for connection via isolation transformer to 10base5 and 10base2, thick and thin based coaxial cables. the twisted-pair transceiver interface allows for connection of unshielded twisted-pair cables as speci?d by the section 14 supplement to ieee 802.3 standard (type 10base-t). important note about the eeprom byte map the user is cautioned that while the AM79C961A (pcnet-isa ii) and its associated eeprom are pin com- patible to their predecessors the am79c961 (pcnet-isa + ) and its associated eeprom, the byte map structure in each of the eeproms are different from each other. the eeprom byte map structure used for the AM79C961A pcnet-isa ii has the addition of ?isc con- ? 2, isacsr9" at word location 10hex. the eeprom byte map structure used for the am79c961 pcnet-isa+ does not have this. therefore, should the user intend to replace the pcnet-isa + with the pcnet-isa ii, care must be taken to reprogram the eeprom to re?ct the new byte map structure needed and used by the pcnet-isa ii. for addi- tional information, refer to the section in this data sheet under eeprom and the am79c961 pcnet-isa + data sheet (pid #18183) under the sections entitled eeprom and serial eeprom byte map . bus master mode system interface the pcnet-isa ii controller has two fundamental oper- ating modes, bus master and bus slave. within the bus slave mode, the pcnet-isa ii can be programmed for a shared memory or programmed i/o architecture. the selection of either the bus master mode or the bus slave mode must be done through hard wiring; it is not software con?urable. when in the bus slave mode, the selection of the shared memory or programmed i/o architecture is done through software with the piosel bit (isacsr2, bit 13). the optional boot prom is in memory address space and is expected to be 8?4k. on-chip address compar- ators control device selection is based on the value in the eeprom. the address prom, board con?uration registers, and the ethernet controller occupy 24 bytes of i/o space and can be located on 16 different starting addresses.
AM79C961A 37 preliminary 19364a-5 eecs isa bus 16-bit system data 24-bit system address pcnet-isa ii controller boot prom (optional) sd[0-15] sa[0-19] la[17-23] bpcs ce oe d[0-7] a[0-15] do di sk cs org eeprom (optional, common) v cc shfbusy v cc prdb[2]/eedo prdb[1]/eedi prdb[0]/eesk prdb[0-7] bus master block diagram plug and play compatible 19364a-6 bus master block diagram plug and play compatible we isa bus 24-bit system address pcnet-isa ii controller ieee address prom (optional) sd[0-15] sa[0-19] la[17-23] prdb[0-7] d[0-7] bpcs a[0-4] sk di do cs oe eeprom (optional, common) eecs flash (optional) prdb[0]/eesk prdb[1]/eedi prdb[2]/eedo g cs org d[0-7] a[0-15] 16-bit system data shfbusy v cc irq15/apcs irq12/flashwe with flash and parallel address prom support v cc
38 AM79C961A preliminary bus slave mode system interface the bus slave mode is the other fundamental operat- ing mode available on the pcnet-isa ii controller. within the bus slave mode, the pcnet-isa ii can be programmed for a shared memory or programmed i/o architecture. in the bus slave mode the pcnet-isa ii controller uses the same descriptor and buffer architec- ture as in the bus master mode, but these data struc- tures are stored in a static ram controlled by the pcnet-isa ii controller. when operating with the shared memory architecture, the local sram is visible as a memory resource on the pc which can be accessed through memory cycles on the isa bus inter- face. when operating with the programmed i/o archi- tecture, the local sram is accessible through i/o cycles on the isa bus. speci?ally, the sram is acces- sible using the rap and idp i/o ports to access the isacsr0 and isacsr1 registers, which serve as the sram data port and sram address pointer port, respectively. in the bus slave mode, the pcnet-isa ii registers and optional ethernet physical address prom look the same and are accessed in the same way as in the bus master mode. the boot prom is selected by an external device which drives the boot prom address match (bp am ) input to the pcnet-isa ii controller. the pcnet-isa ii controller can perform two 8-bit accesses from the 8-bit boot prom and present 16-bits of data to accommo- date 16 bit read accesses on the isa bus. when using the shared memory architecture mode, access to the local sram works the same way as access to the boot prom, with an external device gen- erating the shared memory address match (smam ) signal and the pcnet-isa ii controller performing the sram read or write and the 8/16 bit data conversion. external logic must also drive memcs16 appropriately for the 128kbyte segment decoded from the la[23:17] signals. the programmed i/o architecture mode uses the rap and idp ports to allow access to the local sram hence, external address decoding is not necessary and the smam pin is not used in programmed i/o architec- ture mode (smam should be tied high in the pro- grammed i/o architecture mode). similar to the shared memory architecture mode, in the programmed i/o ar- chitecture mode, 8/16 bit conversion occurs when 16 bit reads and writes are performed on the sram data port (isacsr1). converting the local sram accesses from 8-bit cycles to 16-bit cycles allows use of the much faster 16-bit cycle timing while cutting the number of bus cycles in half. this raises performance to more than 400% of what could be achieved with 8-bit cycles. when the shared memory architecture mode is used, converting boot prom accesses to 16-bit cycles allows the two memory resources to be in the same 128 kbyte block of memory without a clash between two devices with different data widths. the pcnet-isa ii prefetches data from the sram to allow fast, minimum wait-state read accesses of con- secutive sram addresses. in both the shared memory architecture and the programmed i/o architecture, prefetch data is read from a speculated address that assumes that successive reads in time will be from adjacent ascending addresses in the sram. at the beginning of each sram read cycle, the pcnet-isa ii determines whether the prefetched data can be assumed to be valid. if the prefetched data can be assumed to be valid, it is driven onto the isa bus without inserting any wait states. if the prefetched data cannot be assumed to be valid, the pcnet-isa ii will in- sert wait states into the isa bus read cycle until the correct word is read from the sram.
AM79C961A 39 preliminary bus slave block diagram plug and play compatible with flash memory support eecs isa bus 24-bit system address pcnet-isa ii controller prdb[2]/eedo prdb[1]/eedi prdb[0]/eesk 16-bit system data prab[0-15] irq12/srcs v cc d[0-7] d[0?] a[0-15] a[0?5] memcs16 sa[16] la[17-23] v cc note: smam shown only for shared memory architecture designs. smam should be tied high on the pcnet-isa ii for programmed i/o architecture designs. sr we smam smam shfbusy bp am sd[0] sa[0] prdb[0] sr oe bpcs we cs oe sram external glue logic bp am shfbusy sin clk eeprom we cs oe do di sk cs org flash (optional) 19364a-7
40 AM79C961A preliminary plug and play plug and play is a standardized method of con?uring jumperless adapter cards in a system. plug and play is a microsoft standard and is based on a central software con?uration program, either in the operating system or elsewhere, which is responsible for con?uring all plug and play cards in a system. plug and play is fully supported by the pcnet-isa ii ethernet controller. for a copy of the microsoft plug and play speci?ation contact microsoft inc. this speci?ation should be referenced in addition to pcnet-isa ii technical reference manual and this data sheet. operation if the pcnet-isa ii ethernet controller is used to boot off the network, the device will come up active at reset, otherwise it will come up inactive. information stored in the serial eeprom is used to identify the card and to describe the system resources required by the card, such as i/o space, memory space, irqs and dma channels. this information is stored in a standardized read only format. operation of the plug and play system is shown as follows: n isolate the plug and play card n read the cards resource data n identify the card n con?ure its resources the plug and play mode of operation allows the follow- ing benefits to the end user. n eliminates all jumpers or dip switches from the adapter card n ease of use is greatly enhanced n allows the ability to uniquely address identical cards in a system, without con?ct n allows the software con?uration program or os to read out the system resource requirements required by the card n de?es a mechanism to set or modify the current con?uration of each card n maintain backward compatibility with other isa bus adapters auto-con?uration ports three 8 bit i/o ports are used by the plug and play con- guration software on each plug and play device to communicate with the plug and play registers. the ports are listed in the table below. the software con?- uration space is de?ed as a set of 8 bit registers. these registers are used by the plug and play software con?uration to issue commands, access the resource information, check status, and con?ure the pcnet-isa ii controller hardware. the address and write_data ports are located at ?ed, prede?ed i/o addresses. the write_data port is located at an alias of the address port. all three auto-con?uration ports use a 12-bit isa address decode. the read_data port is relocatable within the range 0x203?x3ff by a command written to the write_data port. address port the internal plug and play registers are accessed by writing the address to the address port and then either reading the read_data port or writing to the write_data port. once the address port has been written, any number of reads or writes can occur without having to rewrite the address port. the address port is also the address to which the initiation key is written to, which is described later. write_data port the write_data port is the address to which all writes to the internal plug and play registers occur. the destination of the data written to the write_data port is determined by the last value written to the address port. read_data port the read_data port is used to read information from the internal plug and play registers. the register to be read is determined by the last value of the address port. the i/o address of the read_data port is set by writing the chosen i/o location to plug and play reg- ister 0. the isolation protocol can determine that the address chosen is free from con?ct with other devices i/o ports. initiation key the pcnet-isa ii controller is disabled at reset when operating in plug and play mode. it will not respond to any memory or i/o accesses, nor will the pcnet-isa ii controller drive any interrupts or dma channels. the initiation key places the pcnet-isa ii device into the con?uration mode. this is done by writing a pre- de?ed pattern to the address port. if the proper sequence of i/o writes are detected by the pcnet-isa ii device, the plug and play auto-con?uration ports are enabled. this pattern must be sequential, i.e., any port name location type address 0x279 (printer status port) write-only write-data 0xa79 (printer status port + 0x0800) write-only read-data relocatable in range 0x0203-0x03ff read-only
AM79C961A 41 preliminary other i/o access to this i/o port will reset the state machine which is checking the pattern. interrupts should be disabled during this time to eliminate any extraneous i/o cycles. the exact sequence for the initiation key is listed below in hexadecimal. 6a, b5, da, ed, f6, fb, 7d, be df, 6f, 37, 1b, 0d, 86, c3, 61 b0, 58, 2c, 16, 8b, 45, a2, d1 e8, 74, 3a, 9d, ce, e7, 73, 39 isolation protocol a simple algorithm is used to isolate each plug and play card. this algorithm uses the signals on the isa bus and requires lock-step operation between the plug and play hardware and the isolation software. the key element of this mechanism is that each card contains a unique number, referred to as the serial identi?r for the rest of the discussion. the serial iden- ti?r is a 72-bit unique, non-zero, number composed of two, 32-bit ?lds and an 8-bit checksum. the ?st 32-bit ?ld is a vendor identi?r. the other 32 bits can be any value, for example, a serial number, part of a lan address, or a static number, as long as there will never be two cards in a single system with the same 64 bit number. the serial identi?r is accessed bit-serially by the isolation logic and is used to differentiate the cards. the shift order for all plug and play serial isolation and resource data is dened as bit[0], bit[1], and so on through bit[7]. hardware protocol the isolation protocol can be invoked by the plug and play software at any time. the initiation key, described earlier, puts all cards into con?uration mode. the hardware on each card expects 72 pairs of i/o read accesses to the read_data port. the cards response to these reads depends on the value of each bit of the serial identi?r which is being examined one bit at a time in the sequence shown above. if the current bit of the serial identi?r is a ?", then the card will drive the data bus to 0x55 to complete the ?st i/o read cycle. if the bit is ?", then the card puts its data bus driver into high impedance. all cards in high imped- ance will check the data bus during the i/o read cycle to sense if another card is driving d[1:0] to ?1". during the second i/o read, the card(s) that drove the 0x55, will now drive a 0xaa. all high impedance cards will check the data bus to sense if another card is driving d[1:0] to ?0". between pairs of reads, the software should wait at least 30 m s. if a high impedance card sensed another card driving the data bus with the appropriate data during both cycles, then that card ceases to participate in the cur- rent iteration of card isolation. such cards, which lose out, will participate in future iterations of the isolation protocol. note: during each read cycle, the plug and play hard- ware drives the entire 8-bit databus, but only checks the lower 2 bits. state isolation read all 72 bits from serial identifier id bit = ?h sd[1:0] = ?1" wait for next read from serial isolation register sd[1:0] = ?0" state sleep one card isolated read from serial isolation register get one bit from serial identifier yes no no yes drive ?5h on sd[7:0] leave sd in high-impedance leave sd in high-impedance drive ?ah on sd[7:0] no yes no yes after i/o read completes, fetch next id bit from serial identifier id = 0; other card id = 1 19364a-8 plug and play isa card isolation algorithm shifting of serial identifier byte 0 byte 3 byte 2 byte 1 byte 0 byte 3 byte 2 byte 1 byte 0 shift check- sum serial number vendor id 19364a-9
42 AM79C961A preliminary if a card was driving the bus or if the card was in high impedance and did not sense another card driving the bus, then it should prepare for the next pair of i/o reads. the card shifts the serial identifier by one bit and uses the shifted bit to decide its response. the above sequence is repeated for the entire 72-bit serial identifier. at the end of this process, one card remains. this card is assigned a handle referred to as the card select number (csn) that will be used later to select the card. cards which have been assigned a csn will not partic- ipate in subsequent iterations of the isolation protocol. cards must be assigned a csn before they will respond to the other commands defined in the specification. it should be noted that the protocol permits the 8-bit checksum to be stored in non-volatile memory on the card or generated by the on-card logic in real-time. the same lfsr algorithm described in the initiation key section of the plug and play specification is used in the checksum generation. software protocol the plug and play software sends the initiation key to all plug and play cards to place them into configuration mode. the software is then ready to perform the isola- tion protocol. the plug and play software generates 72 pairs of l/o read cycles from the read_data port. the software checks the data returned from each pair of i/o reads for the 0x55 and 0xaa driven by the hardware. if both 0x55 and 0xaa are read back, then the software assumes that the hardware had a ?" bit in that posi- tion. all other results are assumed to be a ?. during the first 64 bits, software generates a checksum using the received data. the checksum is compared with the checksum read back in the last 8 bits of the sequence. there are two other special considerations for the soft- ware protocol. during an iteration, it is possible that the 0x55 and 0xaa combination is never detected. it is also possible that the checksum does not match if either of these cases occur on the first iteration, it must be assumed that the read_data port is in conflict. if a conflict is detected, then the read_data port is relocated. the above process is repeated until a non- conflicting location for the read_data port is found. the entire range between 0x203 and 0x3ff is avail- able, however in practice it is expected that only a few locations will be tried before software determines that no plug and play cards are present. during subsequent iterations, the occurrence of either of these two special cases should be interpreted as the absence of any further plug and play cards (i.e. the last card was found in the previous iteration). this terminates the isolation protocol. note: the software must delay 1 ms prior to starting the first pair of isolation reads, and must wait 250 m sec between each subsequent pair of isolation reads. this delay gives the isa card time to access information from possibly very slow storage devices. plug and play card control registers the state transitions and card control commands for the pcnet-isa ii controller are shown in the following figure.
AM79C961A 43 preliminary 19364a-10 plug and play isa card state transitions lose serial isolation or (wake <> csn) power up reset or reset command active commands state wait for key no active commands sleep active commands state reset wait for key wake[csn] isolation active commands state reset wait for key set rd_data port serial isolation wake[csn] config active commands state reset wait for key wake[csn] resource data status logical device i/o range check activate configuration registers set csn = 0 initiation key set csn (wake = 0) and (csn = 0) (wake 1 0) and (wake = csn) (wake <> csn) notes 1. csn = card select number 2. reset or the reset command causes a state transition from the current state to wait for key and sets all csns to zero. 3. the wait for key command causes a state transition from the current state to wait for key. plug and play registers the pcnet-isa ii controller supports all of the de?ed plug and play card control registers. refer to the tables on the following pages for detailed information.
44 AM79C961A preliminary plug and play standard registers name address port value de?ition set rd_data port 0x00 writing to this location modi?s the address of the port used for reading from the plug and play isa cards. bits [7:0] become i/o read port address bits [9:2] . reads from this register are ignored. i/o address bits 11:10 should = 00, and 1:0 = 11. serial isolation 0x01 a read to this register causes a plug and play card in the isolation state to compare one bit of the boards id. this process is fully described above. this register is read only. con? control 0x02 bit[0] - reset all logical devices and restore con?uration registers to their power-up values. bit[1] - return to the wait for key state bit[2] - reset csn to 0 a write to bit[0] of this register performs a reset function on all logical devices. this resets the contents of con?uration registers to their default state. all cards logical devices enter their default state and the csn is preserved. a write to bit[1] of this register causes all cards to enter the wait for key state but all csns are preserved and logical devices are not affected. a write to bit[2] of this register causes all cards to reset their csn to zero. this register is write-only. the values are not sticky, that is, hardware will automatically clear them and there is no need for software to clear the bits. wake[csn] 0x03 a write to this port will cause all cards that have a csn that matches the write data[7:0] to go from the sleep state to either the isolation state if the write data for this command is zero or the con? state if the write data is not zero. this register is write-only. writing to this register resets the eeprom pointer to the beginning of the plug and play data structure. resource data 0x04 a read from this address reads the next byte of resource information. the status register must be polled until bit[0] is set before this register may be read. this register is read-only. status 0x05 bit[0] when set indicates it is okay to read the next data byte from the resource data register. this register is read-only. card select number 0x06 a write to this port sets a cards csn. the csn is a value uniquely assigned to each isa card after the serial identi?ation process so that each card may be individually selected during a wake [csn] command. this register is read/write. logical device number 0x07 selects the current logical device. this register is read only. the pcnet-isa ii controller has only 1 logical device, and this register contains a value of 0x00
AM79C961A 45 preliminary plug and play logical device con?uration registers the pcnet-isa ii controller supports a subset of the de?ed plug and play logical device control registers. the reason for only supporting a subset of the registers is that the pcnet-isa ii controller does not require as many system resources as plug and play allows. for instance, memory descriptor 2 is not used, as the pcnet-isa ii controller only requires two memory descriptors, one for the boot prom/flash, and one for the sram in shared memory mode. plug and play logical device control registers memory space con?uration i/o space con?urationi/o interrupt con?uration name address port value de?ition activate 0x30 for each logical device there is one activate register that controls whether or not the logical device is active on the isa bus. bit[0], if set, activates the logical device. bits[7:1] are reserved and must be zero. this is a read/write register. before a logical device is activated, i/o range check must be disabled. i/o range check 0x31 this register is used to perform a con?ct check on the i/o port range programmed for use by a logical device. bit[7:2] reserved bit 1[1] enable i/o range check, if set then i/o range check is enabled. i/o range check is only valid when the logical device is inactive. bit[0], if set, forces the logical device to respond to i/o reads of the logical devices assigned i/o range with a 0x55 when i/o range check is in operation. if clear, the logical device drives 0xaa. this register is read/write. name register index de?ition memory base address bits[23:16] descriptor 0 0x40 read/write value indicating the selected memory base address bits[23:16] for memory descriptor 0. this is the boot prom space. memory base address bits [23:16] descriptor 0 0x41 read/write value indicating the selected memory base address bits[15:08] for memory descriptor 0. memory control 0x42 bit[1] speci?s 8/16-bit control. the encoding relates to memory control (bits[4:3]) of the information ?ld in the memory descriptor. bit[0], =0, indicates the next ?ld is used as a range length for decode (implies range length and base alignment of memory descriptor are equal). bit[0] is read-only. memory upper limit address; bits [23:16] or range length; bits [15:08] for descriptor 0 0x43 read/write value indicating the selected memory high address bits[23:16] for memory descriptor 0. if bit[0] of memory control is 0, this is the range length. if bit[0] of memory control is 1, this is considered invalid. memory upper limit bits [15:08] or range length; bits [15:08] for descriptor 0 0x44 read/write value indicating the selected memory high address bits[15:08] for memory descriptor 0, either a memory address or a range length as described above. memory descriptor 1 0x48-0x4c memory descriptor 1. this is the sram space for shared memory. name register index de?ition i/o port base address bits[15:08] descriptor 0 0x60 read/write value indicating the selected i/o lower limit address bits[15:08] for i/o descriptor 0. if a logical device indicates it only uses 10 bit encoding, then bits[15:10] do not need to be supported.
46 AM79C961A preliminary dma channel con?uration detailed functions eeprom interface the eeprom supported by the pcnet-isa ii controller is an industry standard 93c56 2-kbit eeprom device which uses a 4-wire interface. this device directly inter- faces to the pcnet-isa ii controller through a 4-wire interface which uses 3 of the private data bus pins for data in, data out, and serial clock. the chip select pin is a dedicated pin from the pcnet-isa ii controller. note : all data stored in the eeprom is stored in bit-reversal format. each word (16 bits) must be written into the eeprom with bit 15 swapped with bit 0, bit 14 swapped with bit 1, etc. this is a 2-kbit device organized as 128 x 16 bit words. a map of the device as used in the pcnet-isa ii con- troller is below. the information stored in the eeprom is as follows: important note about the eeprom byte map the user is cautioned that while the AM79C961A (pcnet-isa ii) and its associated eeprom are pin compatible to their predecessors the am79c961 (pcnet-isa + ) and its associated eeprom, the byte map structure in each of the eeproms are different from each other. the eeprom byte map structure used for the AM79C961A pcnet-isa ii has the addition of ?isc cong 2, isacsr9" at word location 10hex. the eeprom byte map structure used for the am79c961 pcnet-isa+ does not have this. therefore, should the user intend to replace the pcnet-isa + with the pcnet-isa ii, care must be taken to reprogram the eeprom to re?ct the new byte map structure needed and used by the pcnet-isa ii. for additional information, refer to the am79c961 pcnet-isa + data sheet (pid #18183) under the sec- tions entitled eeprom and serial eeprom byte map . i/o port base address bits[07:00] descriptor 0 0x61 read/write value indicating the selected i/o lower limit address bits[07:00] for i/o descriptor 0. name register index de?ition interrupt request level select 0 0x70 read/write value indicating selected interrupt level. bits[3:0] select which interrupt level used for interrupt 0. one selects irql 1, ?teen selects irql ?teen. irql 0 is not a valid interrupt selection and represents no interrupt selection. interrupt request type select 0 0x71 read/write value indicating which type of interrupt is used for the request level selected above. bit[1] : level, 1 = high ,0=low bit[0] : type, 1 = level , 0 = edge the pcnet-isa ii controller only supports edge high and level low interrupts. name register index de?ition name register index de?ition dma channel select 0 0x74 read/write value indicating selected dma channels. bits[2:0] select which dma channel is in use for dma 0. zero selects dma channel 0, seven selects dma channel 7. dma channel 4, the cascade channel is used to indicate no dma channel is active. dma channel select 1 0x75 read only with a value of 0x04. ieee address 6 bytes reserved10 bytes eisa id4 bytes isacsrs14 bytes plug and play defaults19 bytes 8-bit checksum1 byte external shift chain2 bytes plug and play con? info192 bytes
AM79C961A 47 preliminary basic eeprom byte map the following is a byte map of the xxc56 series of eeproms used by the pcnet-isa ii ethernet controller. this byte map is for the case where a non-pcnet family compatible software driver is implemented. note: checksum is calculated on words 0 through 0x1bh (first 56 bytes). byte 1 byte 3 byte 5 byte 7 byte 9 byte 11 byte 13 byte 15 eisa byte 1 eisa byte 3 byte 0 byte 2 byte 4 byte 6 byte 8 byte 10 byte 12 byte 14 eisa byte 0 eisa byte 2 msrda, isacsr0 mswra, isacsr1 misc config 1, isacsr2 led1 config, isacsr5 led2 config, isacsr6 led3 config, isacsr7 misc config 2, isacsr9 pnp 0x61 pnp 0x71 unused pnp 0x41 pnp 0x43 unused pnp 0x49 pnp 0x4b unused 8?it checksum pnp 0x60 pnp 0x70 pnp 0x74 pnp 0x40 pnp 0x42 pnp 0x44 pnp 0x48 pnp 0x4a pnp 0x4c pnp 0xf0 external shift chain unused locations plug and play starting location ieee address (0h) (8h) internal registers (11h) plug and play reg. (1ah) (20h) eisa config reg. (ah) (1bh) (1ch) 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1b 1c 20 . . 1f word location i/o ports interrupts dma channels rom memory ram memory vendor byte (bytes 0 ?5)
48 AM79C961A preliminary amd device driver compatible eeprom byte map the following is a byte map of the xxc56 series of eeproms used by the pcnet-isa ii ethernet controller. this byte map is for the case where a pcnet family compatible software driver is imple- mented. (this byte map is an application reference for use in developing amd software devices.) note: checksum 1 is calculated on words 0 through 5 plus word 7. checksum 2 is calculated on words 0 through 0x1bh (?st 56 bytes). ieee address internal registers plug and play reg. see appendix c eisa config reg. 0 1 2 3 4 5 6 7 8 9 a b c d e f 11 12 13 14 15 16 17 18 19 1a 1b 1c 20 . . 1f word location i/o ports interrupts dma channels rom memory ram memory vendor byte see appendix c (bytes 0?) byte 1 byte 3 byte 5 ascii w (0 x 57h) eisa byte 1 eisa byte 3 byte 0 byte 2 byte 4 ascii w (0 x 57h) eisa byte 0 eisa byte 2 msrda, isacsr0 mswra, isacsr1 misc config, isacr2 led1 config, isacsr5 led2 config, isacsr6 led3 config, isacsr7 misc config 2, isacsr9 pnp 0x61 pnp 0x71 unused pnp 0x41 pnp 0x43 unused pnp 0x49 pnp 0x4b unused 8-bit checksum pnp 0x60 pnp 0x70 pnp 0x74 pnp 0x40 pnp 0x42 pnp 0x44 pnp 0x48 pnp 0x4a pnp 0x4c pnp 0xf0 external shift chain unused locations plug and play starting location user space 1 16-bit checksum 1 reserved hwid (01h) reserved reserved 10
AM79C961A 49 preliminary plug and play register map the following chart and its bit descriptions show the internal con?uration registers associated with the plug and play operation. these registers control the con?uration of the pcnet-isa ii controller. plug and play register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 read_data 0x01 serial isolation 0x02 0 0 0 0 0 rst wait rst csn key all 0x03 wake [csn] 0x04 resource_data 0x05 0 0 0 0 0 0 0 read status 0x06 csn 0x07 logical device number 0x30 0 0 0 0 0 0 0 activate 0x31 0 0 0 0 0 0 iorng iorng read_data address of plug and play read_data port. serial_isolation used in the serial isolation process. rst_csn resets csn register to zero. wait_key resets wait for key state. rst_all resets all logical devices. wake [csn] will wake up if write data matches csn register. read_status read status of resource data. resource_data next pending byte read from eeprom. csn plug and play csn value. activate indicates that the pcnet-isa ii device should be activated. iorng bits used to enable the i/o range check command.
50 AM79C961A preliminary the following chart and its bit descriptions show the internal command registers associated with the plug and play operation. these registers control the pcnet-isa ii controller plug and play operation. pcnet?sa iis legacy bit feature description the current pcnet-isa ii chip is designed such that it always responds to plug and play con?uration soft- ware. there are situations where this response to the plug and play software is undesirable. an example of this is when a ?ed con?uration is required, or when the only possible resource available for the pcnet-isa ii con?cts with a present but not used resource such as irq, or when the chip is used in a system with a buggy pnp bios. to function in the situations above, a new feature has been added to the pcnet-isa ii chip. this new feature makes the chip ignore the pnp softwares special initi- ation key sequence (6a). this will effectively turn the chip into the ?egacy mode operation, where it will be visible in the i/o space, and only special setup pro- grams will be able to recon?ure it. in case the eeprom is missing, empty, or corrupted, the chip will still recognize amds special initiation key sequence (6b). to enable this feature, a one has to be written into the lgcy_en bit, which is bit 6 of the plug and play regis- ter 0xf0. a preferred method would be set this bit in the vendor byte (pnp 0xf0) ?ld of the eeprom located in word offset 0x1a. plug and play register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x60 0 0 0 0 0 0 1 ioam3 0x61 ioam2 ioam1 ioam0 0 0 0 0 0 0x70 0 0 0 0 irq3 irq2 irq1 irq0 0x71 0 0 0 0 0 0 irq_lvl irq_type 0x74 0 0 0 0 0 dma2 dma1 dma0 0x40 0 0 0 0 1 1 0 bpam3 0x41 bpam2 bpam1 bpam0 0 0 0 0 0 0x42 0 0 0 0 0 0 bp_16b 0 0x43 1 1 1 1 1 1 1 bpsz3 0x44 bpsz2 bpsz1 bpsz0 0 0 0 0 0 0x48 0 0 0 0 1 1 sram4 sram3 0x49 sram2 sram1 sram0 0 0 0 0 0 0x4a 0 0 0 0 0 0 sr16b 0 0x4b 1 1 1 1 1 1 1 srsz3 0x4c srsz2 srsz1 srsz0 0 0 0 0 0 0xf0 0 lgcy_en dxcvrp fl_sel bp_cs aprom_en aen_cs io_mode
AM79C961A 51 preliminary plug & play register locations detailed description (refer to the plug & play register map above). ioam[3:0] i/o address match to bits [8:5] of sa bus (pnp 0x60?x61). controls the base address of pcnet-isa ii. the ioam will be written with a value from the eeprom. irq[3:0] irq selection on the isa bus (pnp 0x70). controls which interrupt will be asserted. isa edge sensitive or eisa level mode is controlled by irq_type bit in pnp 0x71. default is isa edge sensitive. the irq sig- nals will not be driven unless pnp activate register bit is set. irq type irq type(pnp 0x71). indicates the type of interrupt setting; level is 1, edge is 0. irq_lvl irq level (pnp 0x71). a read-only register bit that indicates the type of setting, active high or low. always complement of irq_type. dma[2:0] dma channel select (pnp 0x74). controls the drq and dma selec- tion of pcnet-isa ii. the dma[2:0] register will be written with a value from the eeprom. {for bus master mode only} the drq signals will not be driven unless plug and play activate register bit is set. bpam[3:0] boot prom address match to bits [16:13] of sa bus (pnp 0x40?x41). selects the location where the boot prom address match decode is started. the bpam will be written with a value from the eeprom. bp_16b boot prom 16-bit access (pnp 0x42). is asserted if boot prom cycles should respond as an 16-bit device. in bus master mode, all boot prom cycles will only be 8 bits in width. bpsz[3:0] boot prom size (pnp 0x43?x44). selects the size of the boot prom selected. sram[4:0] static ram address match to bits [17:13] of sa bus (pnp 0x48-0x49). selects the starting location of the shared memory when using the ioam[3:0] base address (hex) 0 0 0 0 200 0 0 0 1 220 0 0 1 0 240 0 0 1 1 260 0 1 0 0 280 0 1 0 1 2a0 0 1 1 0 2c0 0 1 1 1 2e0 1 0 0 0 300 1 0 0 1 320 1 0 1 0 340 1 0 1 1 360 1 1 0 0 380 1 1 0 1 3a0 1 1 1 0 3c0 1 1 1 1 3e0 irq[3:0] isa irq pin 0 0 1 1 irq3 (default) 0 1 0 0 irq4 0 1 0 1 irq5 1 0 0 1 irq9 1 0 1 0 irq10 1 0 1 1 irq11 1 1 0 1 irq12 1 1 1 0 irq15 dma[2:0] dma channel (drq/dack pair) 0 1 1 channel 3 1 0 1 channel 5 1 1 0 channel 6 1 1 1 channel 7 1 0 0 no dma channel bpam[3:0] address location (hex) size supported (k bytes) 0000 c0000 8, 16, 32, 64 0001 c2000 8 0010 c4000 8, 16 0011 c6000 8 0100 c8000 8, 16, 32 0101 ca000 8 0110 cc000 8, 16 0111 ce000 8 1000 d0000 8, 16, 32, 64 1001 d2000 8 1010 d4000 8, 16 1011 d6000 8 1100 d8000 8, 16, 32 1101 d a000 8 1110 dc000 8, 16 1111 de000 8 bpsz[3:0] boot prom size 0 x x x no boot prom selected 11118 k 111016 k 110032 k 100064 k
52 AM79C961A preliminary shared memory architecture mode. the sram[2:0] bits are used for per- forming address decoding on the sa[15:13] address bits as shown in the table below. sram[4] and sram[3] must re?ct the external address match logic for sa[17] and sa[16], respectively. the sram[4:0] bits are ignored when in the bus master mode or in the programmed i/o architecture mode. sr_16b static ram 16-bit access (pnp 0x4a). if asserted, the pcnet-isa ii will respond to sram cycles as a 16-bit device. this bit should be set if external logic is designed to assert the memcs16 signal when accesses to the shared memory are decoded. this bit is ignored when in the bus master mode or in the pro- grammed i/o architecture mode. srsz[3:0] static ram size (pnp 0x4b-0x4c). selects the size of the static ram. the srsz[3:0] bits are ignored when in the bus master mode or in the programmed i/o architecture mode. vendor de?ed byte (pnp 0xf0) lgcy_en legacy mode enable. when written with a one, the pcnet-isa ii will not respond to the plug and play initia- tion key sequence (6a) but will respond to the amd key sequence (6b). therefore, it cannot be recon- gured by the plug and play soft- ware. when set to zero (default), the pcnet-isa ii will respond to the 6a key sequence if the eeprom read was successful, otherwise it will re- spond to the 6b key sequence. dxcvrp dxcvr polarity. the dxcvrp bit sets the polarity of the dxcvr pin. when dxcvrp is cleared (default), the dxcvr pin is driven high when the twisted pair port is active or sleep mode has been entered and driven low when the aui port is active. when dxcvrp is set, the dxcvr pin is driven low when the twisted pair port is active or sleep mode has been entered and driven high when the aui port is active. the dxcvrp should generally be left cleared when the pcnet-isa ii is being used with an external dc-dc converter that has an active low enable pin. the dxcvrp should generally be set when the pcnet-isa ii is being used with an external dc-dc converter that has an active high enable pin. io_mode i/o mode. when set to one, the internal selection will respond as a 16-bit port, (i.e. drive iocs16 pin). when io_mode is set to zero, (default), the internal i/o selection will respond as an 8-bit port. aen_cs external decode logic for i/o reg- isters. when written with a one, the pcnet-isa ii will use the aen pin as i/o chip select bar, to allow for exter- nal decode logic for the upper ad- dress bit of sa [9:5]. the purpose of this pin is to allow i/o locations, not supported with the ioam[3:0], selection, to be de?ed outside the range 0x200?x3f7. when set to a zero, (default), i/o selection will use ioam[3:0]. aprom_en external parallel ieee address prom. when set, the irq15 pin is recon?ured to be an address chip select low, similar to apcs pin in the existing pcnet-isa (am79c960) device. the purpose of this bit is to allow for both a serial eeprom and parallel prom to coexist. when aprom_en is set, the ieee address located in the serial ee- prom will be ignored and parallel access will occur over the prdb bus. when aprom_en is cleared, sram[2:0] sa[15:13] sram size (k bytes) 0000008, 16, 32, 64 0010018 0100108, 16 0110118 1001008, 16, 32 1011018 1101108, 16 111 1118 srsz[3:0] shared memory size 0 x x x no static ram selected 1111 8 k 1110 16 k 1100 32 k 1000 64 k
AM79C961A 53 preliminary default state, the ieee address will be read in from the serial device and written to an internal ram. when the i/o space of the ieee prom is selected, pcnet-isa ii, will access the contents of this ram for i/o read cycles. i/o write cycles will be ignored. bp_cs boot prom chip select. when bp_cs is set to one, bale will act as an external chip select (active low) above bit 15 of the address bus. bale = 0, will select the boot prom when memr is asserted low if the bp_cs bit is set and bpam[2:0] match sa[15:13] and bpsz[3:0] matches the selected size. when bp_cs is set to zero. bale will act as the normal address latch strobe to capture the upper address bits for memory access to the boot prom. bp_cs is by default low. the pri- mary purpose of this bit is to allow non-isa bus applications to support larger boot proms or non-standard boot prom/flash locations. fl_sel flash memory device selected. when set, the boot prom is replaced with an external flash memory device. in bus master mode, bpcs is replaced with flash _oe . irq12 becomes flash _we . the flashs cs pin is grounded. in shared memory mode, bpcs is replaced with flash _cs . irq12 becomes static _ram _cs pin. the sr oe and sr we signals are connected to both the sram and flash memory devices. fl_sel is cleared by a reset, which is the default. checksum failure after reset, the pcnet-isa ii controller begins reading the eeprom and storing the information in registers inside pcnet-isa ii controller. pcnet-isa ii controller does a checksum on word locations 0-1bh inclusive and if the byte checksum = ffh, then the data read from the eeprom is considered good. if the checksum is not equal to ffh, then the pcnet-isa ii controller enters what is called software relocatable mode. in software relocatable mode, the device functions the same as in plug and play mode, except that it does not respond to the same initiation key as plug and play supports. instead, a different key is used to bring pcnet-isa ii controller out of the wait for key state. this key is as follows: 6b, 35, 9a, cd, e6, f3, 79, bc 5e, af, 57, 2b, 15, 8a, c5, e2 f1, f8, 7c, 3e, 9f, 4f, 27, 13 09, 84, 42, a1, d0, 68, 34, 1a use without eeprom in some designs, especially pc motherboard applica- tions, it may be desirable to eliminate the eeprom altogether. this would save money, space, and power consumption. the operation of this mode is similar to when the pcnet-isa ii controller encounters a checksum error, except that to enter this mode the shfbusy pin is left unconnected. the device will enter software relocat- able mode, and the bios on the motherboard can wake up the device, con?ure it, load the ieee address (possibly stored in flash rom) into the pcnet-isa ii controller, and activate the device. external scan chain the external scan chain is a set of bits stored in the eeprom which are not used in the pcnet-isa ii con- troller but which can be used with external hardware to allow jumperless con?uration of external devices. after reset, the pcnet-isa ii controller begins reading the eeprom and storing the informa- tion in registers inside the pcnet-isa ii controller. shfbusy is held high during the read of the eeprom. if external circuitry is added, such as a shift register, which is clocked from sclk and is attached to do from the eeprom, data read out of the eeprom will be shifted into the shift register. after reading the eeprom to the end of the external shift chain, and if there is a correct checksum, shfbusy will go low. this will be used to latch the information from the eeprom into the shift register. if the checksum is invalid, shfbusy will not go low, indicating that the eeprom may be bad. flash prom use instead of using a prom or eprom for the boot prom, it may be desirable to use a flash or eeprom type of device for storing the boot code. this would allow for in-system updates and changes to the infor- mation in the boot rom without opening up the pc. it may also be desirable to store statistics or drivers in the flash device. interface to use a flash-type device with the pcnet-isa ii controller, flash select is set in register 0f0h of the
54 AM79C961A preliminary plug and play registers. flash select is cleared by reset (default). in bus master mode, bpcs becomes flash _oe and irq12 becomes flash _we . the flash rom devices cs pin is connected to ground. in shared memory mode, bpcs becomes flash _cs and irq12 becomes the static ram chip select, and the sr oe and sr we signals are connected to both the sram and flash devices. optional ieee address prom normally, the ethernet physical address will be stored in the eeprom with the other con?uration data. this reduces the parts count, board space requirements, and power consumption. the option to use a standard parallel 8 bit prom is provided to manufacturers who are concerned about the non-volatile nature of eeproms. to use a 8 bit parallel prom to store the ieee address data instead of storing it in the eeprom, the aprom_en bit is set in the plug and play registers by the eeprom upon reset. irq15 is rede?ed by the setting of this bit to be apcs , or address prom chip select. this pin is connected to an external 8 bit prom, such as a 27ls19. the address pins of the prom are connected to the lower address pins of the isa bus, and the data lines are connected to the private data bus. in this mode, any accesses to the ieee address will be passed to the external prom and the data will be passed through the pcnet-isa ii controller to the system data bus. eisa con?uration registers the pcnet-isa ii controller has support for the 4-byte eisa con?uration registers. these are used in eisa systems to identify the card and load the appropriate con?uration ?e for that card. this feature is enabled using bit 10 of isacsr2. when set to 1, the eisa con- ?uration registers will be enabled and will be read at i/o location 0xc80?xc83. the contents of these 4 registers are stored in the eeprom and are automat- ically read in at reset. bus interface unit (biu) the bus interface unit is a mixture of a 20 mhz state machine and asynchronous logic. it handles two types of accesses; accesses where the pcnet-isa ii control- ler is a slave and accesses where the pcnet-isa ii con- troller is the current master. in slave mode, signals like iocs16 are asserted and deasserted as soon as the appropriate inputs are received. iochrdy is asynchronously driven low if the pcnet-isa ii controller needs a wait state. it is released synchronously when the pcnet-isa ii control- ler is ready. when the pcnet-isa ii controller is the current master, all the signals it generates are synchronous to the on-chip 20 mhz clock. dma transfers the biu will initiate dma transfers according to the type of operation being performed. there are three pri- mary types of dma transfers: 1. initialization block dma transfers during initialization, the pcnet-isa ii transfers 12 words from the initialization block in memory to internal registers. these 12 words are transferred through dif- ferent bus mastership period sequences, depending on whether the timer bit (csr4, bit 13) is set and, if timer is set, on the value in the bus activity timer register (csr82). if the timer bit is reset (default), the 12 words are always transferred during three separate bus master- ship periods. during each bus mastership period, four words (8 bytes) will be read from contiguous memory addresses. if the timer bit is set, the 12 words may be transferred using anywhere from 1 to 3 bus mastership periods, depending on the value of the bus activity timer regis- ter (csr82). during each bus mastership period, a minimum of four words (8 bytes) will be read from con- tiguous memory addresses. if the timer bit is set and the value in the bus activity timer register allows it, 8 or all 12 words of the initialization block are read during a single bus mastership period. 2. descriptor dma transfers descriptor dma transfers are performed to read or write to transmit or receive descriptors. all transmit and receive descriptor read accesses require 3 word reads (tmd1, tmd0, then tmd2 for transmit descrip- tors and rmd1, rmd0, then rmd2 for receive descrip- tors). transmit and receive descriptor write accesses to unchained descriptors or the last descriptor in a chain (enp set) require 2 word writes (tmd1 then tmd3 for transmit and rmd1 then rmd3 for receive). transmit and receive descriptor write accesses to chained descriptors that do not have enp set require 1 word write (tmd1 for transmit and rmd1 for receive). during descriptor write accesses, only the bytes which need to be written are written, as controlled by the sa0 and sbhe pins. if the timer bit is reset (default), all accesses during a single bus mastership period will be either all read or all write and will be to only one descriptor. hence, when the timer bit is reset, the bus mastership periods for descriptor accesses are always either 3, 2, or 1 cycles
AM79C961A 55 preliminary long, depending on which descriptor operation is being performed. if the timer bit is set, the 3, 2, or 1 cycles required in a descriptor access may be performed as a part of a bus mastership period in which any combination of descriptor reads and writes and buffer reads and writes are performed. when the timer bit is set, the bus activity timer (csr82) and the bus access require- ments of the pcnet-isa ii govern the operations per- formed during a single bus mastership period. 3. fifo dma transfers fifo dma transfers occur when the pcnet-isa ii microcode determines that transfers to and/or from the fifos are required. once the pcnet-isa ii biu has been granted bus mastership, it will perform a series of consecutive transfer cycles before relinquishing the bus. when the bus activity timer is disabled by clearing the timer (csr4, bit 13) bit, all fifo dma transfers within a bus mastership period will be either read or write cycles, and all transfers will be to adjacent, ascending addresses. when the bus activity timer is enabled by setting the timer bit, dma transfers within a bus mastership period may consist of any mixture of read and write cycles, without restriction on the address ordering. this mode of operation allows the pcnet-isa ii to accomplish more during each bus ownership period. the number of data transfer cycles contained within a single bus mastership period is in general dependent on the programming of the dmaplus (csr4, bit 14) and the timer (csr4, bit 13) options. several other factors will also affect the length of the bus mastership period. the possibilities are as follows: if dmaplus = 0 and timer = 0, a maximum of 16 transfers to or from the fifo will be performed by default. this default value may be changed by writing to the dma burst register (csr80, bits 7:0). since timer = 0, all fifo dma transfers within a bus mas- tership period will be either read or write cycles, and all transfers will be to adjacent, ascending addresses. note that dmaplus = 0 merely sets a maximum value for the number of fifo transfers that may occur during one bus mastership period. the minimum number of transfers in the bus mastership period will be deter- mined by the settings of the fifo watermarks and the conditions of the fifos, and the value of the bus activ- ity timer (csr82) if the timer bit is set. if dmaplus = 1 and timer = 0, the bus mastership period will continue until the transmit fifo is ?led to its high threshold (read transfers) or the receive fifo is emptied to its low threshold (write transfers). other variables may also affect the end point of the bus mas- tership period in this mode, including the particular conditions existing within the fifos, and receive and transmit status conditions. since timer = 0, all fifo dma transfers within a bus mastership period will be either read or write cycles, and all transfers will be to adjacent, ascending addresses. if timer = 1, the bus mastership period will continue until all ?ending bus operations are completed or until the bus activity timer value (csr82) has expired. these bus operations may consist of any mixture of descriptor and buffer read and write accesses. if dma- plus = 1, ?ending bus operations includes any de- scriptor accesses and buffer accesses that need to be performed. if dmaplus = 0, ?ending bus operations include any descriptor accesses that need to be per- formed and any buffer accesses that need to be per- formed up to the limit speci?d by the dma burst register (csr80, bits 7:0). note that when timer=1, following a last bus transac- tion during a bus mastership period, the pcnet-isa ii may keep ownership of the bus for up to approximately 1 m s. the pcnet-isa ii determines whether there are further pending bus operations by waiting approxi- mately 1 m s after the completion of every bus operation (e.g. a descriptor or fifo access). if, during the 1 m s period, no further bus operations are requested by the internal buffer management unit, the pcnet-isa ii determines that there are no further pending opera- tions and gives up bus ownership. this 1 m s of unused bus ownership time is more than made up for by the ef?iency gained by being able to perform any mixture of descriptor and buffer read and write accesses during a single bus ownership period. the fifo thresholds are programmable (see descrip- tion of csr80), as are the dma burst register and bus activity timer values. the exact number of transfer cycles in the case of dmaplus = 1 will be dependent on the latency of the system bus to the pcnet-isa ii controllers dma request and the speed of bus opera- tion, but will be limited by the value in the bus activity timer register (if the timer bit is set), the fifo condi- tion, and receive and transmit status. barring a time-out by either of these registers, or exceptional receive and transmit events, or an end of packet signal from the fifo, the fifo watermark settings and the extent of bus grant latency will be the major factors determining the number of accesses performed during any given arbitration cycle when dmaplus = 1. the iochrdy response of the memory device will also affect the number of transfers when dmaplus = 1, since the speed of the accesses will affect the state of the fifo. during accesses, the fifo may be ?ling or emptying on the network end. a slower memory response will allow additional data to accumulate inside of the fifo (during write transfers from the receive fifo). if the accesses are slow enough, a com- plete word may become available before the end of the arbitration cycle and thereby increase the number of
56 AM79C961A preliminary transfers in that cycle. the general rule is that the longer the bus grant latency or the slower the bus transfer operations (or clock speed) or the higher the transmit watermark or the lower the receive watermark or any combination thereof, the longer will be the aver- age bus mastership period. buffer management unit (bmu) the buffer management unit is a microcoded 20 mhz state machine which implements the initialization block and the descriptor architecture. initialization pcnet-isa ii controller initialization includes the read- ing of the initialization block in memory to obtain the operating parameters. the initialization block is read when the init bit in csr0 is set. the init bit should be set before or concurrent with the strt bit to insure cor- rect operation. see previous section ?. initialization block dma transfer. once the initialization block has been read in and processed, the bmu knows where the receive and transmit descriptor rings are. on com- pletion of the read operation and after internal registers have been updated, idon will be set in csr0, and an interrupt generated if iena is set. the initialization block is vectored by the contents of csr1 (least signi?ant 16 bits of address) and csr2 (most signi?ant 8 bits of address). the block contains the user de?ed conditions for pcnet-isa ii controller operation, together with the address and length infor- mation to allow linkage of the transmit and receive descriptor rings. there is an alternative method to initialize the pcnet-isa ii controller. instead of initialization via the initialization block in memory, data can be written directly into the appropriate registers. either method may be used at the discretion of the programmer. if the registers are written to directly, the init bit must not be set, or the initialization block will be read in, thus over- writing the previously written information. please refer to appendix d for details on this alternative method. reinitialization the transmitter and receiver section of the pcnet-isa ii controller can be turned on via the initialization block (mode register dtx, drx bits; csr15[1:0]). the state of the transmitter and receiver are monitored through csr0 (rxon, txon bits). the pcnet-isa ii controller should be reinitialized if the transmitter and/ or the receiver were not turned on during the original initialization and it was subsequently required to acti- vate them, or if either section shut off due to the detec- tion of an error condition (merr, uflo, tx buff error). reinitialization may be done via the initialization block or by setting the stop bit in csr0, followed by writing to csr15, and then setting the start bit in csr0. note that this form of restart will not perform the same in the pcnet-isa ii controller as in the lance. in par- ticular, the pcnet-isa ii controller reloads the transmit and receive descriptor pointers (working registers) with their respective base addresses. this means that the software must clear the descriptors own bits and reset its descriptor ring pointers before the restart of the pcnet-isa controller. the reload of descriptor base addresses is performed in the lance only after initial- ization, so a restart of the lance without initialization leaves the lance pointing at the same descriptor locations as before the restart. suspend the pcnet-isa ii controller offers a suspend mode that allows easy updating of the csr registers without going through a full reinitialization of the device. the suspend mode also allows stopping the device with orderly termination of all network activity. the host requests the pcnet-isa ii controller to enter the suspend mode by setting spnd (csr5, bit 0) to one. the host must poll spnd until it reads back one to determine that the pcnet-isa ii controller has en- tered the suspend mode. when the host sets spnd to one, the pcnet-isa ii controller ?st ?ishes all on-going transmit activity and updates the correspond- ing transmit descriptor entries. it then ?ishes all on-going receive activity and updates the correspond- ing receive descriptor entries. it then sets the read-version of spnd to one and enters the suspend mode. in suspend mode, all of the csr registers are accessible. as long as the pcnet-isa ii controller is not reset while in suspend mode (by asserting the reset pin, reading the reset register, or by setting the stop bit), no reinitialization of the device is required after the device comes out of suspend mode. when spnd is set to zero, the pcnet-isa ii controller will leave the suspend mode and will continue at the trans- mit and receive descriptor ring locations where it had left when it entered the suspend mode. buffer management buffer management is accomplished through message descriptor entries organized as ring structures in mem- ory. there are two rings, a receive ring and a transmit ring. the size of a message descriptor entry is 4 words (8 bytes). descriptor rings each descriptor ring must be organized in a contiguous area of memory. at initialization time (setting the init bit in csr0), the pcnet-isa ii controller reads the user-de?ed base address for the transmit and receive descriptor rings, which must be on an 8-byte boundary, as well as the number of entries contained in the descriptor rings. by default, a maximum of 128 ring entries is permitted when utilizing the initialization block, which uses values of tlen and rlen to specify
AM79C961A 57 preliminary the transmit and receive descriptor ring lengths. how- ever, the ring lengths can be manually de?ed (up to 65535) by writing the transmit and receive ring length registers (csr76,78) directly. each ring entry contains the following information: n the address of the actual message data buffer in user or host memory n the length of the message buffer n status information indicating the condition of the buffer receive descriptor entries are similar (but not identical) to transmit descriptor entries. both are composed of four registers, each 16 bits wide for a total of 8 bytes. to permit the queuing and de-queuing of message buffers, ownership of each buffer is allocated to either the pcnet-isa ii controller or the host. the own bit within the descriptor status information, either tmd or rmd (see section on tmd or rmd), is used for this purpose. ?eadly embrace conditions are avoided by the ownership mechanism. only the owner is permitted to relinquish ownership or to write to any ?ld in the descriptor entry. a device that is not the current owner of a descriptor entry cannot assume ownership or change any ?ld in the entry. descriptor ring access mechanism at initialization, the pcnet-isa ii controller reads the base address of both the transmit and receive descrip- tor rings into csrs for use by the pcnet-isa ii control- ler during subsequent operation. when transmit and receive functions begin, the base address of each ring is loaded into the current descrip- tor address registers and the address of the next descriptor entry in the transmit and receive rings is computed and loaded into the next descriptor address registers.
58 AM79C961A preliminary polling when there is no channel activity and there is no pre- or post-receive or transmit activity being performed by the pcnet-isa ii controller then the pcnet-isa ii con- troller will periodically poll the current receive and transmit descriptor entries in order to ascertain their ownership. if the dpoll bit in csr4 is set, then the transmit polling function is disabled. a typical polling operation consists of the following: the pcnet-isa ii controller will use the current receive descriptor address stored internally to vector to the appropriate receive descriptor table entry (rdte). it will then use the current transmit descriptor address (stored internally) to vector to the appropriate transmit descriptor table entry (tdte). these accesses will be made to rmd1 and rmd0 of the current rdte and tmd1 and tmd0 of the current tdte at periodic poll- initialization block 24-bit base address pointer to initialization block iadr[15:0] iadr[23:16] res csr1 csr2 tdra[15:0] mode padr[15:0] padr[31:16] padrf[47:32] ladrf[15:0] ladrf[31:16] ladrf[47:32] ladrf[63:48] rdra[15:0] rlen res rdra[23:16] tlen res tdra[23:16] rcv buffers rx descriptor rings rmd0 rmd1 rmd2 rmd3 rcv descriptor ring n n n n 1st desc. start 2nd desc. start rmd0 xmt buffers rx descriptor rings tmd0 tmd1 tmd2 tmd3 rx descriptor rings xmt descriptor ring m m m m 1st desc. start 2nd desc. start tmd0 data buffer 1 data buffer 2 data buffer n data buffer 1 data buffer 2 data buffer m 19364a-11 initialization block and descriptor rings
AM79C961A 59 preliminary ing intervals. all information collected during polling activity will be stored internally in the appropriate csrs. (i.e. csr18?9, csr40, csr20?1, csr42, csr50, csr52). unowned descriptor status will be internally ignored. a typical receive poll occurs under the following conditions: 1. pcnet-isa ii controller does not possess ownership of the current rdte and the poll time has elapsed and rxon = 1, or 2. pcnet-isa ii controller does not possess ownership of the next rdte and the poll time has elapsed and rxon = 1, if rxon = 0, the pcnet-isa ii controller will never poll rdte locations. if rxon = 1, the system should always have at least one rdte available for the possibility of a receive event. when there is only one rdte, there is no polling for next rdte. a typical transmit poll occurs under the following conditions: 1. pcnet-isa ii controller does not possess ownership of the current tdte and dpoll = 0 and txon = 1 and the poll time has elapsed, or 2. pcnet-isa ii controller does not possess ownership of the current tdte and dpoll = 0 and txon = 1 and a packet has just been received, or 3. pcnet-isa ii controller does not possess ownership of the current tdte and dpoll = 0 and txon = 1 and a packet has just been transmitted. the poll time interval is nominally de?ed as 32,768 crystal clock periods, or 1.6 ms. however, the poll time register is controlled internally by microcode, so any other microcode controlled operation will interrupt the incrementing of the poll count register. for example, when a receive packet is accepted by the pcnet-isa ii controller, the device suspends execution of the poll-time-incrementing microcode so that a receive microcode routine may instead be executed. poll-time-incrementing code is resumed when the receive operation has completely ?ished. note, how- ever, that following the completion of any receive or transmit operation, a poll operation will always be per- formed. the poll time count register is never reset. note that if a non-default is desired, then a strict sequence of setting the init bit in csr0, waiting for the idon bit in csr0, then writing to csr47, and then setting strt in csr0 must be observed, otherwise the default value will not be overwritten. see the csr47 section for details. setting the tdmd bit of csr0 will cause the microcode controller to exit the poll counting code and immedi- ately perform a polling operation. if rdte ownership has not been previously established, then an rdte poll will be performed ahead of the tdte poll. transmit descriptor table entry (tdte) if, after a tdte access, the pcnet-isa ii controller ?ds that the own bit of that tdte is not set, then the pcnet-isa ii controller resumes the poll time count and re-examines the same tdte at the next expiration of the poll time count. if the own bit of the tdte is set, but stp = 0, the pcnet-isa ii controller will immediately request the bus in order to reset the own bit of this descriptor; this con- dition would normally be found following a lcol or retry error that occurred in the middle of a transmit packet chain of buffers. after resetting the own bit of this descriptor, the pcnet-isa ii controller will again immediately request the bus in order to access the next tdte location in the ring. if the own bit is set and the buffer length is 0, the own bit will be reset. in the lance the buffer length of 0 is interpreted as a 4096-byte buffer. it is acceptable to have a 0 length buffer on transmit with stp=1 or stp=1 and enp = 1. it is not acceptable to have 0 length buffer with stp = 0 and enp = 1. if the own bit is set and the start of packet (stp) bit is set, then microcode control proceeds to a routine that will enable transmit data transfers to the fifo. if the transmit buffers are data chained (enp = 0 in the rst buffer), then the pcnet-isa ii controller will look ahead to the next transmit descriptor after it has per- formed at least one transmit data transfer from the ?st buffer. more than one transmit data transfer may possi- bly take place, depending upon the state of the trans- mitter. the transmit descriptor look ahead reads tmd0 rst and tmd1 second. the contents of tmd0 and tmd1 will be stored in next tx descriptor address (csr32), next tx byte count (csr66) and next tx status (csr67) regardless of the state of the own bit. this transmit descriptor lookahead operation is performed only once. if the pcnet-isa ii controller does not own the next tdte (i.e. the second tdte for this packet), then it will complete transmission of the current buffer and then
60 AM79C961A preliminary update the status of the current (rst) tdte with the buff and uflo bits being set. if dxsuflo is 0 (bit 6 csr3), then this will cause the transmitter to be dis- abled (csr0, txon = 0). the pcnet-isa ii controller will have to be restarted to restore the transmit function. the situation that matches this description implies that the system has not been able to stay ahead of the pcnet-isa ii controller in the transmit descriptor ring and therefore, the condition is treated as a fatal error. to avoid this situation, the system should always set the transmit chain descriptor own bits in reverse order. if the pcnet-isa ii controller does own the second tdte in a chain, it will gradually empty the contents of the ?st buffer (as the bytes are needed by the transmit operation), perform a single-cycle dma transfer to update the status (reset the own bit in tmd1) of the ?st descriptor, and then it may perform one data dma access on the second buffer in the chain before execut- ing another lookahead operation. (i.e. a lookahead to the third descriptor). the pcnet-isa ii controller can queue up to two pack- ets in the transmit fifo. call them packet ? and packet ?? where ? is after ?? assume that packet ? is currently being transmitted. because the pcnet-isa ii controller can perform lookahead data transfer over an enp, it is possible for the pcnet-isa ii controller to update a tdte in a buffer belonging to packet ? while packet ? is being transmitted if packet ? uses data chaining. this operation will result in non-sequential tdte accesses as packet ? com- pletes transmission and the pcnet-isa ii controller writes out its status, since packet ?s tdte is before the tdte accessed as part of the lookahead data transfer from packet ?? this should not cause any problem for properly written software which processes buffers in sequence, waiting for ownership before proceeding. if an error occurs in the transmission before all of the bytes of the current buffer have been transferred, then tmd2 and tmd1 of the current buffer will be written; in that case, data transfers from the next buffer will not commence. instead, following the tmd2/tmd1 update, the pcnet-isa ii controller will go to the next transmit packet, if any, skipping over the rest of the packet which experienced an error, including chained buffers. this is done by returning to the polling microcode where it will immediately access the next descriptor and nd the condition own = 1 and stp = 0 as described earlier. in that case, the pcnet-isa ii control- ler will reset the own bit for this descriptor and continue in like manner until a descriptor with own = 0 (no more transmit packets in the ring) or own = 1 and stp = 1 (the ?st buffer of a new packet) is reached. at the end of any transmit operation, whether success- ful or with errors, and the completion of the descriptor updates, the pcnet-isa ii controller will always perform another poll operation. as described earlier, this poll operation will begin with a check of the current rdte, unless the pcnet-isa ii controller already owns that descriptor. then the pcnet-isa ii controller will proceed to polling the next tdte. if the transmit descriptor own bit has a zero value, then the pcnet-isa ii controller will resume poll time count incrementation. if the transmit descriptor own bit has a value of one, then the pcnet-isa ii controller will begin ?ling the fifo with transmit data and initiate a transmission. this end-of-operation poll avoids insert- ing poll time counts between successive transmit packets. whenever the pcnet-isa ii controller completes a transmit packet (either with or without error) and writes the status information to the current descriptor, then the tint bit of csr0 is set to indicate the completion of a transmission. this causes an interrupt signal if the iena bit of csr0 has been set and the tintm bit of csr3 is reset. receive descriptor table entry (rdte) if the pcnet-isa ii controller does not own both the cur- rent and the next receive descriptor table entry, then the pcnet-isa ii controller will continue to poll accord- ing to the polling sequence described above. if the receive descriptor ring length is 1, there is no next descriptor, and no look ahead poll will take place. if a poll operation has revealed that the current and the next rdte belongs to the pcnet-isa ii controller, then additional poll accesses are not necessary. future poll operations will not include rdte accesses as long as the pcnet-isa ii controller retains ownership to the cur- rent and the next rdte. when receive activity is present on the channel, the pcnet-isa ii controller waits for the complete address of the message to arrive. it then decides whether to accept or reject the packet based on all active address- ing schemes. if the packet is accepted the pcnet-isa ii controller checks the current receive buffer status register crst (csr40) to determine the ownership of the current buffer. if ownership is lacking, then the pcnet-isa ii controller will immediately perform a (last ditch) poll of the current rdte. if ownership is still denied, then the pcnet-isa ii controller has no buffer in which to store the incoming message. the miss bit will be set in csr0 and an interrupt will be generated if iena = 1 (csr0) and missm = 0 (csr3). another poll of the current rdte will not occur until the packet has ?ished. if the pcnet-isa ii controller sees that the last poll (either a normal poll or the last-ditch effort described in the above paragraph) of the current rdte shows valid ownership, then it proceeds to a poll of the next rdte.
AM79C961A 61 preliminary following this poll, and regardless of the outcome of this poll, transfers of receive data from the fifo may begin. regardless of ownership of the second receive descriptor, the pcnet-isa ii controller will continue to perform receive data dma transfers to the ?st buffer, using burst-cycle dma transfers. if the packet length exceeds the length of the ?st buffer, and the pcnet-isa ii controller does not own the second buffer, ownership of the current descriptor will be passed back to the system by writing a zero to the own bit of rmd1 and status will be written indicating buffer (buff = 1) and possibly over?w (oflo = 1) errors. if the packet length exceeds the length of the ?st (cur- rent) buffer, and the pcnet-isa ii controller does own the second (next) buffer, ownership will be passed back to the system by writing a zero to the own bit of rmd1 when the ?st buffer is full. receive data transfers to the second buffer may occur before the pcnet-isa ii con- troller proceeds to look ahead to the ownership of the third buffer. such action will depend upon the state of the fifo when the status has been updated on the ?st descriptor. in any case, lookahead will be performed to the third buffer and the information gathered will be stored in the chip, regardless of the state of the owner- ship bit. as in the transmit ?w, lookahead operations are performed only once. this activity continues until the pcnet-isa ii controller recognizes the completion of the packet (the last byte of this receive message has been removed from the fifo). the pcnet-isa ii controller will subsequently update the current rdte status with the end of packet (enp) indi- cation set, write the message byte count (mcnt) of the complete packet into rmd2 and overwrite the ?urrent entries in the csrs with the ?ext entries. media access control the media access control engine incorporates the essential protocol requirements for operation of a com- pliant ethernet/802.3 node, and provides the interface between the fifo sub-system and the manchester encoder/decoder (mendec). this section describes operation of the mac engine when operating in half duplex mode. when in half duplex mode, the mac engine is fully compliant to sec- tion 4 of iso/iec 8802-3 (ansi/ieee standard 1990 second edition) and ansi/ieee 802.3 (1985). when operating in full duplex mode, the mac engine behavior changes as described in the full duplex operation sec- tion. the mac engine provides programmable enhanced features designed to minimize host supervision and pre or post-message processing. these features include the ability to disable retries after a collision, dynamic fcs generation on a packet-by-packet basis, and auto- matic pad eld insertion and deletion to enforce minimum frame size attributes. the two primary attributes of the mac engine are: n transmit and receive message data encapsulation framing (frame boundary delimitation, frame synchronization) addressing (source and destination address handling) error detection (physical medium transmission errors) n media access management medium allocation (collision avoidance) contention resolution (collision handling) transmit and receive message data encapsulation the mac engine provides minimum frame size enforcement for transmit and receive packets. when apad_xmt = 1 (bit 11 in csr4), transmit messages will be padded with suf?ient bytes (containing 00h) to ensure that the receiving station will observe an infor- mation eld (destination address, source address, length/type, data and fcs) of 64-bytes. when astrp_rcv = 1 (bit 10 in csr4), the receiver will automatically strip pad bytes from the received mes- sage by observing the value in the length ?ld, and stripping excess bytes if this value is below the mini- mum data size (46 bytes). both features can be inde- pendently over-ridden to allow illegally short (less than 64 bytes of packet data) messages to be transmitted and/or received. the use of these features reduce bus bandwidth usage because the pad bytes are not trans- ferred to or from host memory. framing (frame boundary delimitation, frame synchronization) the mac engine will autonomously handle the con- struction of the transmit frame. once the transmit fifo has been ?led to the predetermined threshold (set by xmtsp in csr80), and providing access to the chan- nel is currently permitted, the mac engine will com- mence the 7-byte preamble sequence (10101010b, where ?st bit transmitted is a 1). the mac engine will subsequently append the start frame delimiter (sfd) byte (10101011b) followed by the serialized data from the transmit fifo. once the data has been completed, the mac engine will append the fcs (most signi?ant bit ?st) which was computed on the entire data portion of the message. note that the user is responsible for the correct order- ing and content in each of the elds in the frame, including the destination address, source address, length/type and packet data. the receive section of the mac engine will detect an incoming preamble sequence and lock to the encoded
62 AM79C961A preliminary clock. the internal mendec will decode the serial bit stream and present this to the mac engine. the mac will discard the ?st 8 bits of information before search- ing for the sfd sequence. once the sfd is detected, all subsequent bits are treated as part of the frame. the mac engine will inspect the length ?ld to ensure min- imum frame size, strip unnecessary pad characters (if enabled), and pass the remaining bytes through the receive fifo to the host. if pad stripping is performed, the mac engine will also strip the received fcs bytes, although the normal fcs computation and checking will occur. note that apart from pad stripping, the frame will be passed unmodi?d to the host. if the length ?ld has a value of 46 or greater, the mac engine will not attempt to validate the length against the number of bytes contained in the message. if the frame terminates or suffers a collision before 64 bytes of information (after sfd) have been received, the mac engine will automatically delete the frame from the receive fifo, without host intervention. addressing (source and destination address handling) the ?st 6 bytes of information after sfd will be inter- preted as the destination address eld. the mac engine provides facilities for physical, logical, and broadcast address reception. in addition, multiple physical addresses can be constructed (perfect address ltering) using external logic in conjunction with the eadi interface. error detection (physical medium transmission errors) the mac engine provides several facilities which report and recover from errors on the medium. in addi- tion, the network is protected from gross errors due to inability of the host to keep pace with the mac engine activity. on completion of transmission, the following transmit status is available in the appropriate tmd and csr areas: n the exact number of transmission retry attempts (one, more, or rtry). n whether the mac engine had to defer (def) due to channel activity. n loss of carrier, indicating that there was an inter- ruption in the ability of the mac engine to monitor its own transmission. repeated lcar errors indicate a potentially faulty transceiver or network connection. n late collision (lcol) indicates that the transmis- sion suffered a collision after the slot time. this is indicative of a badly con?ured network. late colli- sions should not occur in a normal operating net- work. n collision error (cerr) indicates that the trans- ceiver did not respond with an sqe test message within the predetermined time after a transmission completed. this may be due to a failed transceiver, disconnected or faulty transceiver drop cable, or the fact the transceiver does not support this feature (or the feature is disabled). in addition to the reporting of network errors, the mac engine will also attempt to prevent the creation of any network error due to the inability of the host to service the mac engine. during transmission, if the host fails to keep the transmit fifo ?led suf?iently, causing an under?w, the mac engine will guarantee the message is either sent as a runt packet (which will be deleted by the receiving station) or has an invalid fcs (which will also cause the receiver to reject the message). the status of each receive message is available in the appropriate rmd and csr areas. fcs and framing errors (fram) are reported, although the received frame is still passed to the host. the fram error will only be reported if an fcs error is detected and there are a non-integral number of bits in the message. the mac engine will ignore up to seven additional bits at the end of a message (dribbling bits), which can occur under normal network operating conditions. the recep- tion of eight additional bits will cause the mac engine to de-serialize the entire byte, and will result in the received message and fcs being modi?d. the pcnet-isa ii controller can handle up to 7 dribbling bits when a received packet terminates. during the reception, the crc is generated on every serial bit (including the dribbling bits) coming from the cable, although the internally saved crc value is only updated on the eighth bit (on each byte boundary). the framing error is reported to the user as follows: 1. if the number of the dribbling bits are 1 to 7 and there is no crc error, then there is no framing error (fram = 0). 2. if the number of the dribbling bits are less than 8 and there is a crc error, then there is also a framing error (fram = 1). 3. if the number of dribbling bits = 0, then there is no framing error. there may or may not be a crc (fcs) error. counters are provided to report the receive collision count and runt packet count used for network statis- tics and utilization calculations. note that if the mac engine detects a received packet which has a 00b pattern in the preamble (after the ?st 8 bits, which are ignored), the entire packet will be ignored. the mac engine will wait for the network to go inactive before attempting to receive the next packet.
AM79C961A 63 preliminary media access management the basic requirement for all stations on the network is to provide fairness of channel allocation. the 802.3/ ethernet protocol de?es a media access mechanism which permits all stations to access the channel with equality. any node can attempt to contend for the chan- nel by waiting for a predetermined time (inter packet gap interval) after the last activity, before transmitting on the medium. the channel is a multidrop communications medium (with various topological con- gurations permitted) which allows a single station to transmit and all other stations to receive. if two nodes simultaneously contend for the channel, their signals will interact, causing loss of data (de?ed as a collision). it is the responsibility of the mac to attempt to avoid and recover from a collision, to guarantee data integrity for the end-to-end transmission to the receiving station. medium allocation (collision avoidance) the ieee 802.3 standard (iso/iec 8802-3 1990) requires that the csma/cd mac monitor the medium traf? by looking for carrier activity. when carrier is detected the medium is considered busy, and the mac should defer to the existing message. the ieee 802.3 standard also allows optional two part deferral after a receive message. see ansi/ieee std 802.3-1990 edition, 4.2.3.2.1: ?ote : it is possible for the pls carrier sense indication to fail to be asserted during a colli- sion on the media. if the deference process simply times the interpacket gap based on this indication it is possible for a short interframe gap to be generated, leading to a potential re- ception failure of a subsequent frame. to en- hance system robustness the following option- al measures, as specified in 4.2.8, are recom- mended when interframespacingpart1 is other than zero: (1) upon completing a transmission, start timing the interpacket gap, as soon as transmitting and carrier sense are both false. (2) when timing an interpacket gap following re- ception, reset the interpacket gap timing if car- rier sense becomes true during the first 2/3 of the interpacket gap timing interval. during the final 1/3 of the interval the timer shall not be re- set to ensure fair access to the medium. an ini- tial period shorter than 2/3 of the interval is permissible including zero. the mac engine implements the optional receive two part deferral algorithm, with a ?st part inter-frame-spacing time of 6.0 m s. the second part of the inter-frame-spacing interval is therefore 3.6 m s. the pcnet-isa ii controller will perform the two-part deferral algorithm as speci?d in section 4.2.8 (pro- cess deference). the inter packet gap (ipg) timer will start timing the 9.6 m s interframespacing after the receive carrier is de-asserted. during the ?st part deferral (interframespacingpart1 ?ifs1) the pcnet-isa ii controller will defer any pending transmit frame and respond to the receive message. the ipg counter will be reset to zero continuously until the car- rier de-asserts, at which point the ipg counter will resume the 9.6 m s count once again. once the ifs1 period of 6.0 m s has elapsed, the pcnet-isa ii control- ler will begin timing the second part deferral (interframespacingpart2 ?ifs2) of 3.6 m s. once ifs1 has completed, and ifs2 has commenced, the pcnet-isa ii controller will not defer to a receive packet if a transmit packet is pending. this means that the pcnet-isa ii controller will not attempt to receive the receive packet, since it will start to transmit, and gener- ate a collision at 9.6 m s. the pcnet-isa ii controller will guarantee to complete the preamble (64-bit) and jam (32-bit) sequence before ceasing transmission and invoking the random backoff algorithm. in addition, transmit two part deferral is implemented as an option which can be disabled using the dxmt2pd bit (csr3). two-part deferral after transmis- sion is useful for ensuring that severe ipg shrinkage cannot occur in specic circumstances, causing a transmit message to follow a receive message so closely as to make them indistinguishable. during the time period immediately after a transmis- sion has been completed, the external transceiver (in the case of a standard aui connected device), should generate the sqe test message (a nominal 10 mhz burst of 5-15 bit times duration) on the ci pair (within 0.6 m s ?1.6 m s after the transmission ceases). during the time period in which the sqe test message is expected the pcnet-isa ii controller will not respond to receive carrier sense. see ansi/ieee std 802.3-1990 edition, 7.2.4.6 (1): ?t the conclusion of the output function, the dte opens a time window during which it ex- pects to see the signal_quality_erro r signal as- serted on the control in circuit. the time win- dow begins when the carrier_status be- comes carrier_off. if execution of the out- put function does not cause carrier_on to occur, no sqe test occurs in the dte. the du- ration of the window shall be at least 4.0 m s but no more than 8.0 m s. during the time window the carrier sense function is inhibited. the pcnet-isa ii controller implements a carrier sense ?linding period within 0 ?4.0 m s from de-assertion of carrier sense after transmission. this effectively means that when transmit two part deferral is enabled (dxmt2pd is cleared) the ifs1 time is from 4 m s to 6 m s after a transmission. however, since ipg shrinkage below 4 m s will rarely be encountered on a correctly con?ured network, and since the fragment size will be
64 AM79C961A preliminary larger than the 4 m s blinding window, then the ipg counter will be reset by a worst case ipg shrinkage/ fragment scenario and the pcnet-isa ii controller will defer its transmission. in addition, the pcnet-isa ii controller will not restart the ?linding period if carrier is detected within the 4.0 m s ?6.0 m s ifs1 period, but will commence timing of the entire ifs1 period. contention resolution (collision handling) collision detection is performed and reported to the mac engine by the integrated manchester encoder/ decoder (mendec). if a collision is detected before the complete preamble/ sfd sequence has been transmitted, the mac engine will complete the preamble/sfd before appending the jam sequence. if a collision is detected after the pream- ble/sfd has been completed, but prior to 512 bits being transmitted, the mac engine will abort the trans- mission, and append the jam sequence immediately. the jam sequence is a 32-bit all zeroes pattern. the mac engine will attempt to transmit a frame a total of 16 times (initial attempt plus 15 retries) due to nor- mal collisions (those within the slot time). detection of collision will cause the transmission to be re-scheduled, dependent on the backoff time that the mac engine computes. if a single retry was required, the one bit will be set in the transmit frame status (tmd1 in the transmit descriptor ring). if more than one retry was required, the more bit will be set. if all 16 attempts experienced collisions, the rtry bit (in tmd2) will be set (one and more will be clear), and the transmit message will be ?shed from the fifo. if retries have been disabled by setting the drty bit in the mode register (csr15), the mac engine will abandon transmission of the frame on detection of the ?st collision. in this case, only the rtry bit will be set and the transmit message will be ?shed from the fifo. if a collision is detected after 512 bit times have been transmitted, the collision is termed a late collision. the mac engine will abort the transmission, append the jam sequence, and set the lcol bit. no retry attempt will be scheduled on detection of a late collision, and the fifo will be ?shed. the ieee 802.3 standard requires use of a ?runcated binary exponential backoff algorithm which provides a controlled pseudo-random mechanism to enforce the collision backoff interval, before re-transmission is attempted. see ansi/ieee std 802.3-1990 edition, 4.2.3.2.5: ?t the end of enforcing a collision (jamming), the csma/cd sublayer delays before attempt- ing to re-transmit the frame. the delay is an in- teger multiple of slot time. the number of slot times to delay before the nth re-transmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r < 2 k , where k = min (n,10). the pcnet-isa ii controller provides an alternative algorithm, which suspends the counting of the slot time/ipg during the time that receive carrier sense is detected. this algorithm aids in networks where large numbers of nodes are present, and numerous nodes can be in collision. the algorithm effectively acceler- ates the increase in the backoff time in busy networks, and allows nodes not involved in the collision to access the channel while the colliding nodes await a reduction in channel activity. once channel activity is reduced, the nodes resolving the collision time out their slot time counters as normal. manchester encoder/decoder (mendec) the integrated manchester encoder/decoder provides the pls (physical layer signaling) functions required for a fully compliant ieee 802.3 station. the mendec provides the encoding function for data to be transmit- ted on the network using the high accuracy on-board oscillator, driven by either the crystal oscillator or an ex- ternal cmos-level compatible clock. the mendec also provides the decoding function from data received from the network. the mendec contains a power on reset (por) circuit, which ensures that all analog por- tions of the pcnet-isa ii controller are forced into their correct state during power-up, and prevents erroneous data transmission and/or reception during this time. external crystal characteristics when using a crystal to drive the oscillator, the crystal specication shown in the speci?ation table may be used to ensure less than 0.5 ns jitter at do . external crystal characteristics requires trimming crystal spec; no trim is 50 ppm total parameter min nom max unit 1. parallel resonant frequency 20 mhz 2. resonant frequency error (cl = 20 pf) ?0 +50 ppm 3.change in resonant frequency with respect to temperature (0 ?70 c; cl = 20 pf)* ?0 +40 ppm 4. crystal capacitance 20 pf 5. motional crystal capacitance (c1) 0.022 pf 6. series resistance 25 w 7. shunt capacitance 7 pf 8. drive level tbd mw
AM79C961A 65 preliminary external clock drive characteristics when driving the oscillator from an external clock source, xtal2 must be left ?ating (unconnected). an external clock having the following characteristics must be used to ensure less than 0.5 ns jitter at do . mendec transmit path the transmit section encodes separate clock and nrz data input signals into a standard manchester encoded serial bit stream. the transmit outputs (do ) are designed to operate into terminated transmission lines. when operating into a 78 w terminated transmission line, the transmit signaling meets the required output levels and skew for cheapernet, ethernet, and ieee-802.3. transmitter timing and operation a 20 mhz fundamental-mode crystal oscillator pro- vides the basic timing reference for the mendec por- tion of the pcnet-isa ii controller. the crystal input is divided by two to create the internal transmit clock ref- erence. both clocks are fed into the manchester encoder to generate the transitions in the encoded data stream. the internal transmit clock is used by the mendec to internally synchronize the internal trans- mit data (itxdat) from the controller and internal transmit enable (itxen). the internal transmit clock is also used as a stable bit-rate clock by the receive sec- tion of the mendec and controller. the oscillator requires an external 0.005% crystal, or an external 0.01% cmos-level input as a reference. the accuracy requirements, if an external crystal is used, are tighter because allowance for the on-chip oscillator must be made to deliver a ?al accuracy of 0.01%. transmission is enabled by the controller. as long as the itxen request remains active, the serial output of the controller will be manchester encoded and appear at do . when the internal request is dropped by the controller, the differential transmit outputs go to one of two idle states, dependent on tsel in the mode register (csr15, bit 9): receive path the principal functions of the receiver are to signal the pcnet-isa ii controller that there is information on the receive pair, and to separate the incoming manchester encoded data stream into clock and nrz data. the receiver section (see receiver block diagram) consists of two parallel paths. the receive data path is a zero threshold, wide bandwidth line receiver. the carrier path is an offset threshold bandpass detecting line receiver. both receivers share common bias networks to allow operation over a wide input common mode range. input signal conditioning transient noise pulses at the input data stream are rejected by the noise rejection filter. pulse width rejection is proportional to transmit data rate which is ?ed at 10 mhz for ethernet systems but which could be different for proprietary networks. dc inputs more negative than minus 100 mv are also suppressed. the carrier detection circuitry detects the presence of an incoming data packet by discerning and rejecting noise from expected manchester data, and controls the stop and start of the phase-lock loop during clock acquisition. clock acquisition requires a valid manchester bit pattern of 1010b to lock onto the incom- ing message. when input amplitude and pulse width conditions are met at di , a clock acquisition cycle is initiated. clock acquisition when there is no activity at di (receiver is idle), the receive oscillator is phase-locked to stdclk. the ?st negative clock transition (bit cell center of ?st valid manchester ?") after clock acquisition begins inter- rupts the receive oscillator. the oscillator is then restarted at the second manchester ?" (bit time 4) and is phase-locked to it. as a result, the mendec acquires the clock from the incoming manchester bit pattern in 4 bit times with a ?010" manchester bit pat- tern. the internal receiver clock, irxclk, and the internal received data, irxdat, are enabled 1/4 bit time after clock acquisition in bit cell 5. irxdat is at a high state when the receiver is idle (no irxclk). irxdat how- ever, is unde?ed when clock is acquired and may remain high or change to low state whenever irx- clk is enabled. at 1/4 bit time through bit cell 5, the controller portion of the pcnet-isa ii controller sees the rst irxclk transition. this also strobes in the incoming ?th bit to the mendec as manchester ?". irxdat may make a transition after the irxclk rising edge in bit cell 5, but its state is still unde?ed. the manchester ?" at bit 5 is clocked to irxdat output at 1/4 bit time in bit cell 6. clock frequency: 20 mhz 0.01 % rise/fall time (tr/tf): < 6 ns from 0.5 v to v dd ?.5 xtal1 high/low time (thigh/tlow): 40 ?60% duty cycle xtal1 falling edge to falling edge jitter: < 0.2 ns at 2.5 v input (vdd/2) tsel low: the idle state of do yields ?ero differential to operate transformer-coupled loads tsel high: in this idle state, do+ is positive with respect to do?(logical high).
66 AM79C961A preliminary pll tracking after clock acquisition, the phase-locked clock is com- pared to the incoming transition at the bit cell center (bcc) and the resulting phase error is applied to a cor- rection circuit. this circuit ensures that the phase-locked clock remains locked on the received signal. individual bit cell phase corrections of the voltage controlled oscillator (vco) are limited to 10% of the phase difference between bcc and phase- locked clock. receiver block diagram carrier tracking and end of message the carrier detection circuit monitors the di inputs after irxcrs is asserted for an end of message. irxcrs de-asserts 1 to 2 bit times after the last posi- tive transition on the incoming message. this initiates the end of reception cycle. the time delay from the last rising edge of the message to irxcrs deassert allows the last bit to be strobed by irxclk and transferred to the controller section, but prevents any extra bit(s) at the end of message. when irxcrs de-asserts an irxcrs hold off timer inhibits irxcrs assertion for at least 2 bit times. data decoding the data receiver is a comparator with clocked output to minimize noise sensitivity to the di inputs. input error is less than 35 mv to minimize sensitivity to input rise and fall time. irxclk strobes the data receiver output at 1/4 bit time to determine the value of the manchester bit, and clocks the data out on irxdat on the following irxclk. the data receiver also generates the signal used for phase detector compari- son to the internal mendec voltage controlled oscillator (vco). differential input terminations the differential input for the manchester data (di ) should be externally terminated by two 40.2 w 1% resistors and one optional common-mode bypass capacitor, as shown in the differential input termination diagram below. the differential input impedance, z idf , and the common-mode input impedance, z icm , are specied so that the ethernet speci?ation for cable termination impedance is met using standard 1% resistor terminators. if sip devices are used, 39 w is the nearest usable equivalent value. the ci differen- tial inputs are terminated in exactly the same way as the di pair. collision detection a mau detects the collision condition on the network and generates a differential signal at the ci inputs. this collision signal passes through an input stage which detects signal levels and pulse duration. when the signal is detected by the mendec it sets the inter- nal collision signal, iclsn, high. the condition contin- ues for approximately 1.5 bit times after the last low-to-high transition on ci . data receiver manchester decoder noise reject filter carrier detect circuit *internal signal di irxdat* irxclk* irxcrs* 19364a-12 pcnet-isa ii di+ di 40.2 w 40.2 w 0.01 m f to 0.1 m f aui isolation transformer differential input termination 19364a-13
AM79C961A 67 preliminary jitter tolerance de?ition the mendec utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. the clock acquisition circuitry requires four valid bits with the values 1010b. clock is phase-locked to the nega- tive transition at the bit cell center of the second ?" in the pattern. since data is strobed at 1/4 bit time, manchester tran- sitions which shift from their nominal placement through 1/4 bit time will result in improperly decoded data. with this as the criteria for an error, a de?ition of ?itter handling is: the peak deviation approaching or crossing 1/4 bit cell position from nominal input transi- tion, for which the mendec section will properly decode data. attachment unit interface (aui) the aui is the pls (physical layer signaling) to pma (physical medium attachment) interface which con- nects the dte to a mau. the differential interface pro- vided by the pcnet-isa ii controller is fully compliant with section 7 of iso 8802-3 (ansi/ieee 802.3). after the pcnet-isa ii controller initiates a transmis- sion, it will expect to see data ?ooped-back on the di pair (when the aui port is selected). this will internally generate a ?arrier sense? indicating that the integrity of the data path to and from the mau is intact, and that the mau is operating correctly. this ?arrier sense sig- nal must be asserted within sometime before end of transmission. if ?arrier sense does not become active in response to the data transmission, or becomes inac- tive before the end of transmission, the loss of carrier (lcar) error bit will be set in the transmit descriptor ring (tmd3, bit 11) after the packet has been transmitted. twisted pair transceiver (t-mau) this section describes operation of the t-mau when operating in the half duplex mode. when in half duplex mode, the t-mau implements the medium attachment unit (mau) functions for the twisted pair medium as speci?d by the supplement to ieee 802.3 standard (type 10base-t). when operating in full duplex mode, the mac engine behavior changes as described in the full duplex operation section. the t-mau provides twisted pair driver and receiver cir- cuits, including on-board transmit digital predistortion and receiver squelch, and a number of additional fea- tures including link status indication, automatic twisted pair receive polarity detection/correction and indication, receive carrier sense, transmit active and collision present indication. twisted pair transmit function the differential driver circuitry in the txd and txp pins provides the necessary electrical driving capability and the pre-distortion control for transmitting signals over maximum length twisted pair cable, as speci?d by the 10base-t supplement to the ieee 802.3 stan- dard. the transmit function for data output meets the propagation delays and jitter speci?d by the standard. twisted pair receive function the receiver complies with the receiver speci?ations of the ieee 802.3 10base-t standard, including noise immunity and received signal rejection criteria (?mart squelch?. signals meeting these criteria appearing at the rxd differential input pair are routed to the mendec. the receiver function meets the propagation delays and jitter requirements speci?d by the stan- dard. the receiver squelch level drops to half its thresh- old value after unsquelch to allow reception of minimum amplitude signals and to offset carrier fade in the event of worst case signal attenuation conditions. note that the 10base-t standard de?es the receive input amplitude at the external media dependent inter- face (mdi). filter and transformer loss are not speci- ?d. the t-mau receiver squelch levels are designed to account for a 1 db insertion loss at 10 mhz for the type of receive ?ters and transformers usually used. normal 10base-t compatible receive thresholds are invoked when the lrt bit (csr15, bit 9) is low. when the lrt bit is set, the low receive threshold option is invoked, and the sensitivity of the t-mau receiver is increased. increasing t-mau sensitivity allows the use of lines longer than the 100 m target distance of stan- dard 10base-t (assuming typical 24 awg cable). increased receiver sensitivity compensates for the increased signal attenuation caused by the additional cable distance. however, making the receiver more sensitive means that it is also more susceptible to extraneous noise, pri- marily caused by coupling from co-resident services (crosstalk). for this reason, end users may wish to invoke the low receive threshold option on 4-pair cable only. multi-pair cables within the same outer sheath have lower crosstalk attenuation, and may allow noise emitted from adjacent pairs to couple into the receive pair, and be of suf?ient amplitude to falsely unsquelch the t-mau. link test function the link test function is implemented as specied by 10base-t standard. during periods of transmit pair inactivity,?ink beat pulses will be periodically sent over the twisted pair medium to constantly monitor medium integrity.
68 AM79C961A preliminary when the link test function is enabled (dlnktst bit in csr15 is cleared), the absence of link beat pulses and receive data on the rxd pair will cause the tmau to go into the link fail state. in the link fail state, data transmission, data reception, data loopback and the collision detection functions are disabled and remain disabled until valid data or greater than 5 consecutive link pulses appear on the rxd pair. during link fail, the link status (lnkst indicated by led0 ) signal is inactive. when the link is identi?d as functional, the lnkst signal is asserted, and led0 output will be activated. upon power up or assertion of the reset pin, the t-mau will be forced into the link fail state. reading the reset register of the pcnet-isa + (soft- ware reset) has no effect on the t-mau in order to inter-operate with systems which do not implement link test, this function can be disabled by setting the dlnktst bit. with link test disabled, the data driver, receiver and loopback functions as well as collision detection remain enabled irrespective of the presence or absence of data or link pulses on the rxd pair. link test pulses continue to be sent regard- less of the state of the dlnktst bit. polarity detection and reversal the t-mau receive function includes the ability to invert the polarity of the signals appearing at the rxd pair if the polarity of the received signal is reversed (such as in the case of a wiring error). this feature allows data packets received from a reverse wired rxd input pair to be corrected in the t-mau prior to transfer to the mendec. the polarity detection func- tion is activated following reset or link fail, and will reverse the receive polarity based on both the polarity of any previous link beat pulses and the polarity of sub- sequent packets with a valid end transmit delimiter (etd). when in the link fail state, the t-mau will recognize link beat pulses of either positive or negative polarity. exit from the link fail state occurs at the reception of 5 ?6 consecutive link beat pulses of identical polarity. on entry to the link pass state, the polarity of the last 5 link beat pulses is used to determine the initial receive polarity con?uration and the receiver is recon?ured to subsequently recognize only link beat pulses of the previously recognized polarity. positive link beat pulses are de?ed as transmitted sig- nal with a positive amplitude greater than 585 mv with a pulse width of 60 ns ?200 ns. this positive excursion may be followed by a negative excursion. this de?ition is consistent with the expected received signal at a cor- rectly wired receiver, when a link beat pulse, which ?s the template of figure 14-12 of the 10base-t stan- dard, is generated at a transmitter and passed through 100 m of twisted pair cable. negative link beat pulses are de?ed as transmitted signals with a negative amplitude greater than 585 mv with a pulse width of 60 ns ?200 ns. this negative excursion may be followed by a positive excursion. this de?ition is consistent with the expected received sig- nal at a reverse wired receiver, when a link beat pulse which ts the template of figure 14-12 in the 10base-t standard is generated at a transmitter and passed through 100 m of twisted pair cable. the polarity detection/correction algorithm will remain ?rmed until two consecutive packets with valid etd of identical polarity are detected. when ?rmed, the receiver is capable of changing the initial or previous polarity con?uration according to the detected etd polarity. on receipt of the ?st packet with valid etd following reset or link fail, the t-mau will use the inferred polarity information to con?ure its rxd input, regardless of its previous state. on receipt of a second packet with a valid etd with correct polarity, the detection/correction algorithm will ?ock-in the received polarity. if the sec- ond (or subsequent) packet is not detected as con?m- ing the previous polarity decision, the most recently detected etd polarity will be used as the default. note that packets with invalid etd have no effect on updat- ing the previous polarity decision. once two consecu- tive packets with valid etd have been received, the t-mau will lock the correction algorithm until either a link fail condition occurs or reset is asserted. during polarity reversal, an internal pol signal will be active. during normal polarity conditions, this internal pol signal is inactive. the state of this signal can be read by software and/or displayed by led when enabled by the led control bits in the isa bus con?- uration registers (isacsr5, 6, 7). twisted pair interface status three internal signals (xmt, rcv and col) indicate whether the t-mau is transmitting, receiving, or in a collision state. these signals are internal signals and the behavior of the led outputs depends on how the led output circuitry is programmed. the t-mau will power up in the link fail state and the normal algorithm will apply to allow it to enter the link pass state. in the link pass state, transmit or receive activity will be indicated by assertion of rcv signal going active. if t-mau is selected using the portsel bits in csr15, when moving from aui to t-mau selec- tion, the t-mau will be forced into the link fail state. in the link fail state, xmt, rcv and col are inactive. collision detect function activity on both twisted pair signals rxd and txd constitutes a collision, thereby causing the col signal to be asserted. (col is used by the led control cir- cuits) col will remain asserted until one of the two col-
AM79C961A 69 preliminary liding signals changes from active to idle. col stays active for 2 bit times at the end of a collision. signal quality error (sqe) test (heartbeat) function the sqe function is disabled when the 10base-t port is selected and in link fail state. jabber function the jabber function inhibits the twisted pair transmit function of the t-mau if the txd circuit is active for an excessive period (20 ms?50 ms). this prevents any one node from disrupting the network due to a ?tuck-on or faulty transmitter. if this maximum transmit time is exceeded, the t-mau transmitter circuitry is dis- abled, the jab bit is set (csr4, bit 1), and the col sig- nal asserted. once the transmit data stream to the t-mau is removed, an ?njab time of 250 ms ?750 ms will elapse before the t-mau deasserts col and re-enables the transmit circuitry. power down the t-mau circuitry can be made to go into low power mode. this feature is useful in battery powered or low duty cycle systems. the t-mau will go into power down mode when reset is active, coma mode is active, or the t-mau is not selected. refer to the power down mode section for a description of the various power down modes. any of the three conditions listed above resets the internal logic of the t-mau and places the device into power down mode. in this mode, the twisted pair driver pins (txd ,txp ) are asserted low, and the internal t-mau status signals (lnkst, rcvpol, xmt, rcv and collision) are inactive. once the sleep pin is deasserted, the t-mau will be forced into the link fail state. the t-mau will move to the link pass state only after 5? link beat pulses and/ or a single received message is detected on the rxd pair. in snooze mode, the t-mau receive circuitry will remain enabled even while the sleep pin is driven low. the t-mau circuitry will always go into power down mode if reset is asserted, coma is enabled, or the t-mau is not selected. full duplex operation the pcnet-isa ii supports full duplex operation on the 10base-t, aui, and gpsi ports. full duplex operation allows simultaneous transmit and receive activity on the txd and rxd pairs of the 10base-t port, the do and di pairs of the aui port, and the txdat and rxdat pins of the gpsi port. it is enabled by the fden and auifd bits located in isacsr9. when operating in the full duplex mode, the following changes to device operation are made: bus interface/buffer management unit changes: 1. the rst 64 bytes of every transmit frame are not preserved in the transmit fifo during transmission of the ?st 512 bits transmitted on the network, as described in the transmit exception conditions sec- tion. instead, when full duplex mode is active and a frame is being transmitted, the xmtfw bits (csr80, bits 9, 8) always govern when transmit dma is requested. 2. successful reception of the ?st 64 bytes of every receive frame is not a requirement for receive dma to begin as described in the receive exception conditions section. instead, receive dma will be requested as soon as either the rcvfw threshold (csr80 bits 12, 13) is reached or a complete valid receive frame is in the receive fifo, regardless of length. this receive fifo operation is identical to when the rpa bit (csr124, bit 3) is set during half duplex mode operation. mac engine changes: 1. changes to the transmit deferral mechanism: a. transmission is not deferred while receive is active. b. the inter packet gap (ipg) counter which gov- erns transmit deferral during the ipg between back-to-back transmits is started when transmit activity for the ?st packet ends instead of when transmit and carrier activity ends. 2. when the aui or gpsi port is active, loss of carrier (lcar) reporting is disabled (lcar is still reported when the 10base-t port is active if a packet is transmitted while in the link fail state). 3. the 4.0 m s carrier sense blinding period after a transmission during which the sqe test normally occurs is disabled. 4. when the aui or gpsi port is active, the sqe test error (collision error, cerr) reporting is disabled (cerr is still reported when the 10base-t port is active if a packet is transmitted while in the link fail state). 5. the collision indication input to the mac engine is ignored. t-mau changes: 1. the transmit to receive loopback path in the t-mau is disabled. 2. the collision detect circuit is disabled. 3. the ?eartbeat generation (sqe test function) is disabled.
70 AM79C961A preliminary eadi (external address detection interface) this interface is provided to allow external address ?- tering. it is selected by setting the eadisel bit in isacsr2. this feature is typically utilized for terminal servers, bridges and/or router type products. the use of external logic is required to capture the serial bit stream from the pcnet-isa ii controller, compare it with a table of stored addresses or identi?rs, and perform the desired function. the eadi interface operates directly from the nrz decoded data and clock recovered by the manchester decoder or input to the gpsi, allowing the external address detection to be performed in parallel with frame reception and address comparison in the mac station address detection (sad) block. srdclk is provided to allow clocking of the receive bit stream into the external address detection logic. srdclk runs only during frame reception activity. once a received frame commences and data and clock are available, the eadi logic will monitor the alternating (?,0") preamble pattern until the two ones of the start frame delimiter (?,0,1,0,1,0,1,1") are detected, at which point the sf/bd output will be driven high. after sf/bd is asserted the serial data from srd should be de-serialized and sent to a content address- able memory (cam) or other address detection device. to allow simple serial to parallel conversion, sf/bd is provided as a strobe and/or marker to indicate the delineation of bytes, subsequent to the sfd. this pro- vides a mechanism to allow not only capture and/or de- coding of the physical or logical (group) address, it also facilitates the capture of header information to determine protocol and or inter-networking information. the ear pin is driven low by the external address comparison logic to reject the frame. if an internal address match is detected by comparison with either the physical or logical address ?ld, the frame will be accepted regardless of the condition of ear . incoming frames which do not pass the internal address comparison will continue to be received. this allows approximately 58 byte times after the last desti- nation address bit is available to generate the ear signal, assuming the device is not con?ured to accept runt packets. ear will be ignored after 64 byte times after the sfd, and the frame will be accepted if ear has not been asserted before this time. if runt packet accept is congured, the ear signal must be generated prior to the receive message completion, which could be as short as 12 byte times (assuming 6 bytes for source address, 2 bytes for length, no data, 4 bytes for fcs) after the last bit of the destination address is available. ear must have a pulse width of at least 200 ns. note that setting the prom bit (csr15, bit 15) will cause all receive frames to be received, regardless of the state of the ear input. if the drcupa bit (csr15.b) is set and the logical address (ladrf) is set to zero, only frames which are not rejected by ear will be received. the eadi interface will operate as long as the strt bit in csr0 is set, even if the receiver and/or transmitter are disabled by software (dtx and drx bits in csr15 set). this situation is useful as a power down mode in that the pcnet-isa ii controller will not perform any dma operations; this saves power by not utilizing the isa bus driver circuits. however, external circuitry could still respond to speci? frames on the network to facilitate remote node control. the table below summarizes the operation of the eadi features. internal/external address recognition capabilities general purpose serial interface (gpsi) the pcnet-isa ii controller contains a general purpose serial interface (gpsi) designed for testing the digital portions of the chip. the mendec, aui, and twisted pair interface are by-passed once the device is set up in the special ?est mode for accessing the gpsi functions. although this access is intended only for testing the device, some users may ?d the non-encoded data functions useful in some special applications. note, however, that the gpsi functions can be accessed only when the pcnet-isa ii devices operate as a bus master. the pcnet-isa ii gpsi signals are consistent with the lance digital serial interface. since the gpsi func- tions can be accessed only through a special test mode, expect some loss of functionality to the device when the gpsi is invoked. the aui and 10base-t analog interfaces are disabled along with the internal prom ear required timing received messages 1 x no timing requirements all received frames 0 1 no timing requirements all received frames 0 0 low for 200 ns within 512 bits after sfd physical/logical matches
AM79C961A 71 preliminary mendec logic. the la (unlatched address) pins are removed and become the gpsi signals, therefore, only 20 bits of address space is available. the table below shows the gpsi pin con?uration: to invoke the gpsi signals, follow the procedure below: 1. after reset or i/o read of reset address, write 10b to portsel bits in csr15. 2. set the entst bit in csr4 3. set the gpsien bit in csr124 (see note below) (the pins la17?a23 will change function after the completion of the above three steps.) 4. clear the entst bit in csr4 5. clear media select bits in isacsr2 6. dene the portsel bits in the mode register (csr15) to be 10b to de?e gpsi port. the mode register image is in the initialization block. note: la pins will be tristated before writing to gpsien bit. after writing to gpsien, la[17?1] will be inputs, la[22?3] will be outputs. gpsi pin con?urations note: the gpsi function is available only in the bus master mode of operation. gpsi function gpsi i/o type lance gpsi pin pcnet-isa ii gpsi pin pcnet-isa ii pin number pcnet-isa ii normal pin function receive data i rx rxdat 5 la17 receive clock i rclk srdclk 6 la18 receive carrier sense i rena rxcrs 7 la19 collision i clsn clsn 9 la20 transmit clock i tclk stdclk 10 la21 transmit enable o tena txen 11 la22 transmit data o tx txdat 12 la23
72 AM79C961A preliminary ieee 1149.1 test access port interface an ieee 1149.1 compatible boundary scan test access port is provided for board-level continuity test and diag- nostics. all digital input, output, and input/output pins are tested. analog pins, including the aui differential driver (do ) and receivers (di , ci ), and the crystal input (xtal1/xtal2) pins, are tested. the t-mau drivers txd , txp , and receiver rxd are also tested. the following is a brief summary of the ieee 1149.1 compatible test functions implemented in the pcnet-isa ii controller. boundary scan circuit the boundary scan test circuit requires four extra pins (tck, tms, tdi and tdo), de?ed as the test access port (tap). it includes a ?ite state machine (fsm), an instruction register, a data register array, and a power-on reset circuit. internal pull-up resistors are provided for the tdi, tck, and tms pins. the tck pin must not be left unconnected. the boundary scan cir- cuit remains active during sleep. tap fsm the tap engine is a 16-state fsm, driven by the test clock (tck) and the test mode select (tms) pins. this fsm is in its reset state at power-up or reset. an independent power-on reset circuit is provided to ensure the fsm is in the test_logic_reset state at power-up. supported instructions in addition to the minimum ieee 1149.1 requirements (bypass, extest and sample instructions), three additional instructions (idcode, tribyp and setbyp) are provided to further ease board-level testing. all unused instruction codes are reserved. see the table below for a summary of supported instructions. instruction register and decoding logic after hardware or software reset, the idcode instruction is always invoked. the decoding logic gives signals to control the data ow in the data registers according to the current instruction. boundary scan register (bsr) each bsr cell has two stages. a ?p-?p and a latch are used in the serial shift stage and the paral- lel output stage, respectively. there are four possible operational modes in the bsr cell: other data registers (1) bypass reg (1 bit) (2) dev id reg (32 bits ieee 1149.1 supported instruction summary power saving modes the pcnet-isa ii controller supports two hardware power-savings modes. both are entered by asserting the sleep pin low. in coma mode, the pcnet-isa ii controller will go into deep sleep with no support to automatically wake itself up. sleep mode is enabled when the awake bit in isacsr2 is reset. this mode is the default powerdown mode. in snooze mode, enabled by setting the awake bit in isacsr2 and driving the sleep pin low, the t-mau receive circuitry will remain enabled even while the sleep pin is driven low. the led0 output will also continue to function, indicating a good 10base-t link if 1 capture 2 shift 3 update 4 system function bits 31?8: version bits 27?2: part number (2261h) bits 11?: manufacturer id. the 11 bit manufacturer id code for amd is 00000000001 according to jedec publication 106-a. bit 0: always a logic 1 instruction name description selected data reg mode instruction code extest external test bsr test 0000 idcode id code inspection id reg normal 0001 sample sample boundary bsr normal 0010 tribyp force tristate bypass normal 0011 setbyp control boundary to 1/0 bypass test 0100 bypass bypass scan bypass normal 1111
AM79C961A 73 preliminary there are link beat pulses or valid frames present. this led0 pin can be used to drive a led and/or external hardware that directly controls the sleep pin of the pcnet-isa ii controller. this con?uration effectively wakes the system when there is any activity on the 10base-t link. access operations (software) we begin by describing how byte and word data are addressed on the isa bus, including conversion cycles where 16-bit accesses are turned into 8-bit accesses because the resource accessed did not support 16-bit operations. then we describe how registers and other resources are accessed. this section is for the device programmer, while the next section (bus cycles) is for the hardware designer. i/o resources the pcnet-isa ii controller has both i/o and memory resources. in the i/o space the resources are orga- nized as indicated in the following table: the pcnet-isa ii controller does not respond to any addresses outside of the offset range 0-17h. i/o offsets 18h and up are not used by the pcnet-isa ii controller. i/o register access the register address port (rap) is shared by the regis- ter data port (rdp) and the isacsr data port (idp) to save registers. to access the ethernet controllers rdp or idp, the rap should be written ?st, followed by the read or write access to the rdp or idp. i/o register accesses should be coded as 16-bit accesses, even if the pcnet-isa ii controller is hardware con?ured for 8-bit i/o bus cycles. it is acceptable (and transparent) for the motherboard to turn a 16-bit software access into two separate 8-bit hardware bus cycles. the moth- erboard accesses the low byte before the high byte and the pcnet-isa ii controller has circuitry to speci?ally support this type of access. the reset register causes a reset when read. any value will be accepted and the cycle may be 8 or 16 bits wide. writes are ignored. all pcnet-isa ii controller register accesses should be coded as 16-bit operations. ?ote that the rap is cleared on reset. ieee address access the address prom may be an external memory device that contains the nodes unique physical ether- net address and any other data stored by the board manufacturer. the software accesses must be 16-bit. this information may be stored in the eeprom. boot prom access the boot prom is an external memory resource located by the address selected by the eeprom or the bp am input in slave mode. it may be software accessed as an 8-bit or 16-bit resource but the latter is recommended for best performance. static ram access the static ram is only present in the bus slave mode. in the bus slave mode, two sram access schemes are available. when the shared memory architecture mode is selected, the sram is accessed using isa memory cycles to the address range selected by the smam input. it may be accessed as an 8 or 16-bit resource but the latter is recommended for best perfor- mance. when the programmed i/o architecture mode is selected, the sram is accessed through isacsr0 and isacsr1 using the rap and idp. bus cycles (hardware) the pcnet-isa ii controller supports both 8-bit and 16-bit hardware bus cycles. the following sections out- line where any limitations apply based upon the archi- tecture mode and/or the resource that is being accessed (pcnet-isa ii controller registers, address prom, boot prom, or shared memory sram). for completeness, the following sections are arranged by architecture (bus master mode or bus slave mode). sram resources apply only to bus slave mode. all resources (registers, proms, sram) are pre- sented to the isa bus by the pcnet-isa ii controller. with few exceptions, these resources can be con?- ured for either 8-bit or 16-bit bus cycles. the i/o resources (registers, address prom) are width con?- ured using the eeprom. the memory resources (boot prom, sram) are width con?ured by external hard- ware. for 16-bit memory accesses, hardware external to the pcnet-isa ii controller asserts memcs16 when either of the two memory resources is selected. the isa bus requires that all memory resources within a block of 128 kbytes be the same width, either 8- or 16-bits. the reason for this is that the memcs16 signal is generally a decode of the la 17-23 address lines. 16-bit memory capability is desirable since two 8-bit accesses take the same amount of time as four 16-bit accesses. all accesses to 8-bit resources (which do not return memcs16 or iocs16 ) use sd0-7. if an odd byte is accessed, the current master swap buffer turns on. offset #bytes register 0h 16 ieee address 10h 2 rdp 12h 2 rap(shared by rdp and idp) 14h 2 reset 16h 2 idp
74 AM79C961A preliminary during an odd byte read the swap buffer copies the data from sd0-7 to the high byte. during an odd byte write the current master swap buffer copies the data from the high byte to sd0-7. the pcnet-isa ii control- ler can be con?ured to be an 8-bit i/o resource even in a 16-bit system; this is set by the eeprom. it is rec- ommended that the pcnet-isa ii controller be con?- ured for 8-bit only i/o bus cycles for maximum compatibility with pc/at clone motherboards. when the pcnet-isa ii controller is in an 8-bit system such as a pc/xt, sbhe and iocs16 must be left unconnected (these signals do not exist in the pc/xt). this will force all resources (i/o and memory) to sup- port only 8-bit bus cycles. the pcnet-isa ii controller will function in an 8-bit system only if con?ured for bus slave mode. accesses to 16-bit resources (which do return memcs16 or iocs16 ) use either or both sd0? and sd8?5. a word access is indicated by a0=0 and sbhe =0 and data is transferred on all 16 data lines. an even byte access is indicated by a0=0 and sbhe =1 and data is transferred on sd0?. an odd-byte access is indicated by a0=1 and sbhe =0 and data is trans- ferred on sd8-15. it is illegal to have a0=1 and sbhe =1 in any bus cycle. the pcnet-isa ii controller returns only iocs16 ; memcs16 must be generated by external hardware if desired. the use of memcs16 applies only to shared memory mode. the following table describes all possible types of isa bus accesses, including permanent master as current master and pcnet-isa ii controller as current master. the pcnet-isa ii controller will not work with 8-bit memory while it is current master. any descriptions of 8-bit memory accesses are for when the permanent master is current master . the two byte columns (d0? and d8?5) indicate whether the bus master or slave is driving the byte. cs16 is a shorthand for memcs16 and iocs16 . bus master mode the pcnet-isa ii controller can be con?ured as a bus master only in systems that support bus mastering. in addition, the system is assumed to support 16-bit memory (dma) cycles (the pcnet-isa ii controller does not use the memcs16 signal on the isa bus). this does not preclude the pcnet-isa ii controller from doing 8-bit i/o transfers. the pcnet-isa ii controller will not function as a bus master in 8-bit platforms such as the pc/xt. refresh cycles although the pcnet-isa ii controller is neither an origi- nator or a receiver of refresh cycles, it does need to avoid unintentional activity during a refresh cycle in bus master mode. a refresh cycle is performed as follows: first, the ref signal goes active. then a valid refresh address is placed on the address bus. memr goes ac- tive, the refresh is performed, and memr goes inac- tive. the refresh address is held for a short time and them goes invalid. finally, ref goes inactive. during a refresh cycle, as indicated by ref being active, the pcnet-isa ii controller ignores d a ck if it goes active until it goes inactive. it is necessary to ignore d a ck during a refresh because some motherboards gener- ate a false d a ck at that time. isa bus accesses address prom cycles external prom the address prom is a small (16 bytes) 8-bit prom connected to the pcnet-isa ii controller private data bus. the pcnet-isa ii controller will support only 8-bit isa i/o bus cycles for the address prom; this limita- tion is transparent to software and does not preclude 16-bit software i/o accesses. an access cycle begins r/w a0 sbhe cs16 d0? d8?5 comments rd 0 1 x slave float low byte rd rd 1 0 1 slave float high byte rd with swap rd 0 0 1 slave float 16-bit rd converted to low byte rd rd 1 0 0 float slave high byte rd rd 0 0 0 slave slave 16-bit rd wr 0 1 x master float low byte wr wr 1 0 1 master float high byte wr with swap wr 0 0 1 master master 16-bit wr converted to low byte wr wr 1 0 0 float master high byte wr wr 0 0 0 master master 16-bit wr
AM79C961A 75 preliminary with the permanent master driving aen low, driving the addressess valid, and driving ior active. the pcnet-isa ii controller detects this combination of sig- nals and arbitrates for the private data bus (prdb) if necessary. iochrdy is driven low during accesses to the address prom. when the private data bus becomes available, the pcnet-isa ii controller drives apcs active, releases iochrdy, turns on the data path from prd0-7, and enables the sd0-7 drivers (but not sd8-15). during this bus cycle, iocs16 is not driven active. this condi- tion is maintained until ior goes inactive, at which time the bus cycle ends. data is removed from sd0-7 within 30 ns. address prom cycles using eeprom data default mode. in this mode, the ieee address informa- tion is stored not in an external parallel prom but in the eeprom along with other con?uration information. pcnet-isa ii will respond to i/o reads from the ieee address (the ?st 16 bytes of the i/o map) by supplying data from an internal ram inside pcnet-isa ii. this in- ternal ram is loaded with the ieee address at reset and is write protected. ethernet controller register cycles ethernet controller registers (rap, rdp, idp) are natu- rally 16-bit resources but can be con?ured to operate with 8-bit bus cycles provided the proper protocol is fol- lowed. this means on a read, the pcnet-isa ii control- ler will only drive the low byte of the system data bus; if an odd byte is accessed, it will be swapped down. the high byte of the system data bus is never driven by the pcnet-isa ii controller under these conditions. on a write cycle, the even byte is placed in a holding register. an odd byte write is internally swapped up and aug- mented with the even byte in the holding register to pro- vide an internal 16-bit write. this allows the use of 8-bit i/o bus cycles which are more likely to be compatible with all isa-compatible clones, but requires that both bytes be written in immediate succession. this is accomplished simply by treating the pcnet-isa ii con- troller registers as 16-bit software resources. the motherboard will convert the 16-bit accesses done by software into two sequential 8-bit accesses, an even byte access followed immediately by an odd byte access. an access cycle begins with the permanent master driving aen low, driving the address valid, and driving ior or io w active. the pcnet-isa ii controller detects this combination of signals and drives iochrdy low. iocs16 will also be driven low if 16-bit i/o bus cycles are enabled. when the register data is ready, iochrdy will be released high. this condition is maintained until ior or io w goes inactive, at which time the bus cycle ends. reset cycles a read to the reset address causes an pcnet-isa ii controller reset. this has the same effect as asserting the reset pin on the pcnet-isa + controller (which happens on system power up or on a hard boot) except that the t-mau is not reset. the t-mau will retain its link pass/fail state, disregarding the software reset command. the subsequent write cycle needed in the ne2100 lance based family of ethernet cards is not required but does not have any harmful effects. iocs16 is not asserted in this cycle. isa con?uration register cycles the isa con?uration registers are accessed by plac- ing the address of the desired register into the rap and reading the idp. the isacsr bus cycles are identical to all other pcnet-isa ii controller register bus cycles. boot prom cycles the boot prom is an 8-bit prom connected to the pcnet-isa ii controller private data bus (prdb) and can occupy up to 64k of address space. since the pcnet-isa ii controller does not generate memcs16 , only 8-bit isa memory bus cycles to the boot prom are supported in bus master mode; this limitation is transparent to software and does not preclude 16-bit software memory accesses. a boot prom access cycle begins with the permanent master driving the addresses valid, ref inactive, and memr active. (aen is not involved in memory cycles). the pcnet-isa ii controller detects this combination of signals, drives iochrdy low, and reads a byte out of the boot prom. the data byte read is driven onto the lower sys- tem data bus lines and iochrdy is released. this condition is maintained until memr goes inactive, at which time the access cycle ends. the bpcs signal generated by the pcnet-isa ii con- troller is three 20 mhz clock cycles wide (300 ns). including delays, the boot prom has 275 ns to respond to the bpcs signal from the pcnet-isa ii con- troller. this signal is intended to be connected to the cs pin on the boot prom, with the prom oe pin tied to ground. current master operation current master operation only occurs in the bus master mode. it does not occur in the bus slave mode. there are three phases to the use of the bus by the pcnet-isa ii controller as current master, the obtain phase, the access phase, and the release phase. obtain phase a master mode transfer cycle begins by asserting drq. when the permanent master asserts d a ck , the pcnet-isa ii controller asserts master , signifying it has taken control of the isa bus. the permanent mas- ter tristates the address, command, and data lines
76 AM79C961A preliminary within 60 ns of d a ck going active. the permanent master drives aen inactive within 71 ns of master going active. access phase the isa bus requires a wait of at least 125 ns after master is asserted before the new master is allowed to drive the address, command, and data lines. the pcnet-isa ii controller will actually wait 3 clock cycles or 150 ns. the following signals are not driven by the permanent master and are simply pulled high: bale, iochrdy, iocs16 , memcs16 , srd y . therefore, the pcnet-isa ii controller assumes the memory which it is accessing is 16 bits wide and can complete an access in the time programmed for the pcnet-isa ii controller memr and memw signals. refer to the isa bus con?uration register description section. release phase when the pcnet-isa ii controller is ?ished with the bus, it drives the command lines inactive. 50 ns later, the controller tri-states the command, address, and data lines and drives drq inactive. 50 ns later, the con- troller drives master inactive. the permanent master drives aen active within 71 ns of master going inactive. the permanent master is allowed to drive the command lines no sooner than 60 ns after d a ck goes inactive. master mode memory read cycle after the pcnet-isa ii controller has acquired the isa bus, it can perform a memory read cycle. all timing is generated relative to the 20 mhz clock (network clock). since there is no way to tell if memory is 8-bit or 16-bit or when it is ready, the pcnet-isa ii controller by default assumes 16-bit, 1 wait state memory. the wait state assumption is based on the default value in the msrda register in isacsr0. the cycle begins with sa0-19, sbhe , and la17-23 being presented. the isa bus requires them to be valid for at least 28 ns before a read command and the pcnet-isa ii controller provides one clock or 50 ns of setup time before asserting memr . the isa bus requires memr to be active for at least 219 ns, and the pcnet-isa ii controller provides a default of 5 clocks, or 250 ns, but this can be tuned for faster systems with the master mode read active (msrda) register (see section 2.5.2). also, if iochrdy is driven low, the pcnet-isa ii controller will wait. the wait state counter must expire and iochrdy must be high for the pcnet-isa ii controller to continue. the pcnet-isa ii controller then accepts the memory read data. the isa bus requires all command lines to remain inactive for at least 97 ns before starting another bus cycle and the pcnet-isa ii controller pro- vides at least two clocks or 100 ns of inactive time. the isa bus requires read data to be valid no more than 173 ns after receiving memr active and the pcnet-isa ii controller requires 10 ns of data setup time. the isa bus requires read data to provide at least 0 ns of hold time and to be removed from the bus within 30 ns after memr goes inactive. the pcnet-isa ii con- troller requires 0 ns of data hold time. master mode memory write cycle after the pcnet-isa ii controller has acquired the isa bus, it can perform a memory write cycle. all timing is generated relative to a 20 mhz clock which happens to be the same as the network clock. since there is no way to tell if memory is 8- or 16-bit or when it is ready, the pcnet-isa ii controller by default assumes 16-bit, 1 wait state memory. the wait state assumption is based on the default value in the mswra register in isacsr1. the cycle begins with sa0-19, sbhe , and la17-23 being presented. the isa bus requires them to be valid at least 28 ns before memw goes active and data to be valid at least 22 ns before memw goes active. the pcnet-isa ii controller provides one clock or 50 ns of setup time for all these signals. the isa bus requires memw to be active for at least 219 ns, and the pcnet-isa ii controller provides a default of 5 clocks, or 250 ns, but this can be tuned for faster systems with the master mode write active (mswra) register (isacsr1). also, if iochrdy is driven low, the pcnet-isa ii controller will wait. iochrdy must be high for the pcnet-isa ii controller to continue. the isa bus requires data to be valid for at least 25 ns after memw goes inactive, and the pcnet-isa ii con- troller provides one clock or 50 ns. the isa bus requires all command lines to remain inactive for at least 97 ns before starting another bus cycle. the pcnet-isa ii controller provides at least two clocks or 100 ns of inactive time when bit 4 in isacsr2 is set. the eisa bus requires all command lines to remain inactive for at least 170 ns before starting another bus cycle. when bit 4 in isacsr4 is cleared, the pcnet-isa ii controller provides 200 ns of inactive time. back-to-back dma requests the pcnet-isa ii provides for fair bus bandwidth shar- ing between two bus mastering devices on the isa bus through an adaptive delay which is inserted between back-to-back dma requests. when the pcnet-isa ii requires bus access immedi- ately following a bus ownership period, it ?st checks the status of the three currently unused drq pins. if a
AM79C961A 77 preliminary lower priority drq pin than the one currently being used by the pcnet-isa ii is asserted, the pcnet-isa ii will wait 2.6 m s after the deassertion of d a ck before re-asserting its drq pin. if no lower priority drq pin is asserted, the pcnet-isa ii may re-assert its drq pin after as short as 1.1 m s following d a ck deassertion. the priorities assumed by the pcnet-isa ii are ordered drq3, drq5, drq6, drq7, with drq3 having high- est priority and drq7 having the lowest priority. this priority ordering matches that used by typical isa bus dma controllers. this adaptive delay scheme allows for fair bus band- width sharing when two bus mastering devices, e.g. two pcnet-isa ii devices, are on an isa bus. the con- troller using the higher priority dma channel cannot lock out the controller using the lower priority dma channel because of the 2.6 m s delay that is inserted before drq reassertion when a lower priority drq pin is asserted. when there is no lower priority dma request asserted, the pcnet-isa ii re-requests the bus immediately, providing optimal performance when there is no competition for bus access. bus slave mode the pcnet-isa ii can be con?ured to be a bus slave for systems that do not support bus mastering or require a local memory to tolerate high bus latencies. in the bus slave mode, the i/o map of the pcnet-isa ii is identical to the i/o map when in the bus master mode (see i/o resources section). hence, the address prom, controller registers, and reset port are accessed through i/o cycles on the isa bus. however, the initialization block, descriptor rings, and buffers, which are located in system memory when in the bus master mode, are located in a local sram when in the bus slave mode. the local sram can be accessed by memory cycles on the isa bus (shared memory archi- tecture) or by i/o cycles on the isa bus (programmed i/o mode). address prom cycles external prom the address prom is a small (16 bytes) 8-bit prom connected to the pcnet-isa ii controller private data bus (prdb). the pcnet-isa ii controller will support only 8-bit isa i/o bus cycles for the address prom; this limitation is transparent to software and does not preclude 16-bit software i/o accesses. an access cycle begins with the permanent master driving aen low, driving the addresses valid, and driving ior active. the pcnet-isa ii controller detects this combination of sig- nals and arbitrates for the private data bus if neces- sary. iochrdy is always driven low during address prom accesses. when the private data bus becomes available, the pcnet-isa ii controller drives apcs active, releases iochrdy, turns on the data path from prd0-7, and enables the sd0-7 drivers (but not sd8-15). during this bus cycle, iocs16 is not driven active. this condition is maintained until ior goes inactive, at which time the access cycle ends. data is removed from sd0-7 within 30 ns. the pcnet-isa ii controller will perform 8-bit isa bus cycle operation for all resources (registers, proms, sram) if sbhe has been left unconnected, such as in the case of an 8-bit system like the pc/xt. ethernet controller register cycles ethernet controller registers (rap, rdp, isacsr) are naturally 16-bit resources but can be con?ured to operate with 8-bit bus cycles provided the proper pro- tocol is followed. this is programmable by the eeprom. this means on a read, the pcnet-isa ii con- troller will only drive the low byte of the system data bus; if an odd byte is accessed, it will be swapped down. the high byte of the system data bus is never driven by the pcnet-isa ii controller under these con- ditions. on a write, the even byte is placed in a holding register. an odd-byte write is internally swapped up and augmented with the even byte in the holding register to provide an internal 16-bit write. this allows the use of 8-bit i/o bus cycles which are more likely to be compat- ible with all clones, but requires that both bytes be writ- ten in immediate succession. this is accomplished simply by treating the pcnet-isa ii controller controller registers as 16-bit software resources. the mother- board will convert the 16-bit accesses done by software into two sequential 8-bit accesses, an even-byte access followed immediately by an odd-byte access. an access cycle begins with the permanent master driving aen low, driving the address valid, and driving ior or io w active. the pcnet-isa ii controller detects this combination of signals and drives iochrdy low. iocs16 will also be driven low if 16-bit i/o bus cycles are enabled. when the register data is ready, iochrdy will be released high. this condition is maintained until ior or io w goes inactive, at which time the bus cycle ends. the pcnet-isa ii controller will perform 8-bit isa bus cycle operation for all resources (registers, proms, sram) if sbhe has been left unconnected, such as in the case of an 8-bit system like the pc/xt. reset cycles a read to the reset address causes an pcnet-isa ii controller reset. this has the same effect as asserting the reset pin on the pcnet-isa + controller (which happens on system power up or on a hard boot) except that the t-mau is not reset. the t-mau will retain its link pass/fail state, disregarding the software reset command. the subsequent write cycle needed in the ne2100 lance- based family of ethernet cards is not required but does not have any harmful effects. iocs16 is not asserted in this cycle.
78 AM79C961A preliminary isa con?uration register cycles the isa con?uration register is accessed by placing the address of the desired register into the rap and reading the idp. the isacsr bus cycles are identical to all other pcnet-isa ii controller register bus cycles. boot prom cycles the boot prom is an 8-bit prom connected to the pcnet-isa ii controller private data bus (prdb), and can occupy up to 64 kbytes of address space. in shared memory mode, an external address compara- tor is responsible for asserting bp am to the pcnet-isa ii controller. bp am is intended to be a perfect decode of the boot prom address space, i.e. la17-23, sa16. the la bus must be latched with bale in order to pro- vide stable signal for bp am . ref inactive must be used by the external logic to gate boot prom address decoding. this same logic must assert memcs16 to the isa bus if 16-bit boot prom bus cycles are desired. in the bus slave mode, boot prom cycles can be pro- grammed to be 8 or 16-bit isa memory cycles with the bp_16b bit (pnp 0x42). if the bp_16b bit is set, the pcnet-isa ii assumes 16-bit isa memory cycles for the boot prom. in this case, the external hardware responsible for generating bp am must also generate memcs16 . a 16-bit boot prom bus cycle begins with the permanent master driving the addresses valid and memr active. (aen is not involved in memory cycles). external hardware would assert bp am and memcs16 . the pcnet-isa ii controller detects this combination of signals, drives iochrdy low, and reads two bytes out of the boot prom. the data bytes read from the prom are driven by the pcnet-isa ii controller onto sd0-15 and iochrdy is released. this condition is maintained until memr goes inactive, at which time the access cycle ends. the pcnet-isa ii controller will perform 8-bit isa bus cycle operation for all resource (registers, proms, sram) if sbhe has been left unconnected, such as in the case of an 8-bit system like the pc/xt. the bpcs signal generated by the pcnet-isa ii con- troller is three 20 mhz clock cycles wide (350 ns). including delays, the boot prom has 275 ns to respond to the bpcs signal from the pcnet-isa ii con- troller. this signal is intended to be connected to the cs pin on the boot prom, with the prom oe pin tied to ground. static ram cycles ?shared memory architecture in the shared memory architecture mode, the sram is an 8-bit device connected to the pcnet-isa ii controller private bus, and can occupy up to 64 kbytes of address space. the sram is memory mapped into the isa memory space at an address range determined by external decode logic. the external address compara- tor is responsible for asserting smam to the pcnet-isa ii controller. smam is intended to be a perfect decode of the sram address space, i.e. la17-23, sa16 for 64 kbytes of sram. the la signals must be latched by bale in order to provide a stable decode for smam . the pcnet-isa ii controller assumes 16-bit isa mem- ory bus cycles for the sram, so this same logic must assert memcs16 to the isa bus if 16-bit bus cycles are to be supported. a 16-bit sram bus cycle begins with the permanent master driving the addresses valid, ref inactive, and either memr or memw active. (aen is not involved in memory cycles). external hardware would assert smam and memcs16 . the pcnet-isa ii controller detects this combination of signals and initiates the sram access. in a write cycle, the pcnet-isa ii controller stores the data into an internal holding register, allowing the isa bus cycle to ?ish normally. the data in the holding reg- ister will then be written to the sram without the need for isa bus control. in the event the holding register is already ?led with unwritten sram data, the pcnet-isa ii controller will extend the isa write cycle by driving iochrdy low until the unwritten data is stored in the sram. the current isa bus cycle will then complete normally. in a read cycle, the pcnet-isa ii controller arbitrates for the private bus. if it is unavailable, the pcnet-isa ii controller drives iochrdy low. the pcnet-isa ii controller compares the 16 bits of address on the sys- tem address bus with that of a data word held in an internal pre-fetch register. if the address does not match that of the prefetched sram data, then the pcnet-isa ii controller drives iochrdy low and reads two bytes from the sram. the pcnet-isa ii controller then proceeds as though the addressed data location had been prefetched. if the internal prefetch buffer contains the correct data, then the pre-fetch buffer data is driven on the system data bus. if iochrdy was previously driven low due to either private data bus arbitration or sram access, then it is released high. the pcnet-isa ii controller remains in this state until memr is de-asserted, at which time the pcnet-isa ii controller performs a new prefetch of the sram. in this way memory read wait states can be minimized. the pcnet-isa ii controller performs prefetches of the sram between isa bus cycles. the sram is prefetched in an incrementing word address fashion. prefetched data are invalidated by any other activity on the private bus, including shared memory writes by either the isa bus or the network interface, and also address and boot prom reads.
AM79C961A 79 preliminary the only way to con?ure the pcnet-isa ii controller for 8-bit isa bus cycles for sram accesses is to con- ?ure the entire pcnet-isa ii controller to support only 8-bit isa bus cycles. this is accomplished by leaving the sbhe pin disconnected. the pcnet-isa ii control- ler will perform 8-bit isa bus cycle operation for all resources (registers, proms, sram) if sbhe has never been driven active since the last reset, such as in the case of an 8-bit system like the pc/xt. in this case, the external address decode logic must not assert memcs16 to the isa bus, which will be the case if memcs16 is left unconnected. it is possible to man- ufacture a dual 8/16 bit pcnet-isa ii controller adapter card, as the memcs16 and sbhe signals do not exist in the pc/xt environment. at the memory device level, each sram private bus read cycle takes two 50 ns clock periods for a maxi- mum read access time of 75 ns. the timing looks like this: the address and sr oe go active within 20 ns of the clock going high. data is required to be valid 5 ns before the end of the second clock cycle. address and sr oe have a 0 ns hold time after the end of the second clock cycle. note that the pcnet-isa ii controller does not normally provide a separate sram cs signal; sram cs must always be asserted. sram private bus write cycles require three 50 ns clock periods to guarantee non-negative address setup and hold times with regard to sr we . the timing is illustrated as follows: address and data are valid 20 ns after the rising edge of the ?st clock period. sr we goes active 20 ns after the falling edge of the ?st clock period. sr we goes inactive 20 ns after the falling edge of the third clock period. address and data remain valid until the end of the third clock period. rise and fall times are nominally 5 ns. non-negative setup and hold times for address and data with respect to sr we are guaranteed. sr we has a pulse width of typically 100 ns, minimum 75 ns. static ram cycles ?programmed i/o architecture in the programmed i/o architecture mode, the sram is an 8-bit device connected to the pcnet-isa ii control- ler private bus, and can occupy up to 64 kbytes of address space. the sram is accessed through the isacsr0 and isacsr1 registers which serve as the sram data port and sram address pointer, respec- tively. since the isacsrs are used to access the sram, simple i/o accesses (to rap and idp) which are decoded by the pcnet-isa ii are used to access the sram without any external decoding logic. the rap and idp ports are naturally 16-bit resources and can be accessed with 16-bit isa i/o cycles if the io_mode bit (pnp 0xf0) is set. as discussed in the ethernet controller register cycles section, 8-bit i/o cycles are also allowed, provided the proper protocol is followed. this protocol requires that byte accesses must be performed in pairs, with the even byte access always being followed by associated odd byte access. in the programmed i/o architecture mode, when accessing the sram data port in particular (isacsr0), the restrictions on byte accesses are slightly different. even byte accesses (accesses where a0 = 0, sbhe = 1) may be performed to isacsr0 with- out any restriction. a corresponding odd byte access need not be performed following the even byte access as is required when accessing all other controller reg- isters. in fact, odd byte accesses (accesses where a0 = 1, sbhe = 1) may not be performed to isacsr0, ex- cept when they are the result of a software 16-bit access that are automatically converted to two byte ac- cesses by motherboard logic. since the internal pcnet-isa ii registers are used to access the sram in the programmed i/o architecture mode, the access cycle on the isa bus is identical to that described in the ethernet controller register cycles section. to minimize the number of i/o cycles required to access the sram, the pcnet-isa ii auto-increments the sram address pointer (isacsr1) by one or two following every read or write to the sram data port (isacsr0). if a single byte read or write to the sram data port occurs, the sram address pointer is auto- matically incremented by 1. if a word read or write to the sram data port occurs, the sram address pointer is automatically incremented by 2. this allows xtal1 (20 mhz) address sr oe 19364a-14 static ram read cycle address/ data srwe xtal1 (20 mhz) static ram write cycle 19364a-15
80 AM79C961A preliminary reads and writes to adjacent ascending addresses in the sram to be performed without intervening writes to the sram address pointer. since buffer accesses comprise a high percentage of all accesses to the sram, and buffer accesses are typically performed in adjacent ascending order, the auto-increment of the sram address pointer reduces the required isa bus cycles signi?antly. in addition to the auto-incrementing of the sram address pointer, the pcnet-isa ii performs write post- ing on writes to the sram and read prefetching on reads from the sram to maximize performance in the programmed i/o architecture mode. write posting: when a write cycle to the sram data port occurs, the pcnet-isa ii controller stores the data into an internal holding register, allowing the isa bus cycle to ?ish normally. the data in the holding register will then be written to the sram without the need for isa bus control. in the event that the holding register is already ?led with unwritten sram data, the pcnet-isa ii controller will extend the isa write cycle by driving ochrdy low until the unwritten data is stored in the sram. once the data is written into the sram, the new write data is stored into the internal holding regis- ter and iochrdy is released allowing the isa bus cycle to complete. read prefetching: to gain performance on read accesses to the sram, the pcnet-isa ii performs prefetches of the sram after every read from the sram data port. the prefetch is performed using the speculated address that results from the auto-increment that occurs on the sram address pointer following every access to the sram data port. following every read access, the 16-bit word following the just-read sram byte or word is prefetched and placed in a holding register. if a word read from the sram data port occurs before a ?refetch invalidation event occurs, the prefetched word is driven onto the sd[15:0] pins without a wait state (no iochrdy low assertion). a ?refetch invalidation event is de?ed as any activity on the private bus other than sram reads. this includes sram writes by either the isa bus or the network interface, address or boot prom reads, or any write to the sram address pointer. the pcnet-isa ii interface to the sram in the pro- grammed i/o architecture mode is identical to that in the shared memory architecture mode. hence, the sram read and write cycle descriptions and dia- grams shown in the ?tatic ram cycles ?shared memory architecture section apply. transmit operation the transmit operation and features of the pcnet-isa ii controller are controlled by programmable options. transmit function programming automatic transmit features, such as retry on collision, fcs generation/transmission, and pad ?ld insertion, can all be programmed to provide ?xibility in the (re-)transmission of messages. disable retry on collision (drty) is controlled by the drty bit of the mode register (csr15) in the initializa- tion block. automatic pad ?ld insertion is controlled by the apad_xmt bit in csr4. if apad_xmt is set, auto- matic pad ?ld insertion is enabled, the dxmtfcs fea- ture is over-ridden, and the 4-byte fcs will be added to the transmitted frame unconditionally. if apad_xmt is cleared, no pad ?ld insertion will take place and runt packet transmission is possible. the disable fcs generation/transmission feature can be programmed dynamically on a frame by frame basis. see the add_fcs description of tmd1. transmit fifo watermark (xmtfw in csr80) sets the point at which the bmu (buffer management unit) requests more data from the transmit buffers for the fifo. this point is based upon how many 16-bit bus transfers (2 bytes) could be performed to the existing empty space in the transmit fifo. transmit start point (xmtsp in csr80) sets the point when the transmitter actually tries to go out on the media. this point is based upon the number of bytes written to the transmit fifo for the current frame. when the entire frame is in the fifo, attempts at trans- mission of preamble will commence regardless of the value in xmtsp. the default value of xmtsp is 10b, meaning 64 bytes full. automatic pad generation transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). this allows the minimum frame size of 64 bytes (512 bits) for 802.3/ethernet to be guaranteed with no software inter- vention from the host/controlling process. setting the apad_xmt bit in csr4 enables the automatic pad- ding feature. the pad is placed between the llc data ?ld and fcs ?ld in the 802.3 frame. fcs is always added if the frame is padded, regardless of the state of dxmtfcs. the transmit frame will be padded by bytes with the value of 00h. the default value of apad_xmt is 0, and this will disable auto pad generation after reset. it is the responsibility of upper layer software to cor- rectly dene the actual length ?ld contained in the message to correspond to the total number of llc data bytes encapsulated in the packet (length ?ld as de?ed in the ieee 802.3 standard). the length value contained in the message is not used by the pcnet-isa ii controller to compute the actual number of pad bytes
AM79C961A 81 preliminary to be inserted. the pcnet-isa ii controller will append pad bytes dependent on the actual number of bits transmitted onto the network. once the last data byte of the frame has completed prior to appending the fcs, the pcnet-isa ii controller will check to ensure that 544 bits have been transmitted. if not, pad bytes are added to extend the frame size to this value, and the fcs is then added. the 544 bit count is derived from the following: minimum frame size (excluding preamble, including fcs) 64 bytes 512 bits preamble/sfd size 8 bytes 64 bits fcs size 4 bytes 32 bits to be classed as a minimum-size frame at the receiver, the transmitted frame must contain: preamble + (min frame size + fcs) bits at the point that fcs is to be appended, the transmitted frame should contain: preamble + (min frame size - fcs) bits 64+ (512- 32) bits a minimum-length transmit frame from the pcnet-isa ii controller will, therefore, be 576 bits after the fcs is appended. transmit fcs generation automatic generation and transmission of fcs for a transmit frame depends on the value of dxmtfcs bit in csr15. when dxmtfcs = 0 the transmitter will generate and append the fcs to the transmitted frame. if the automatic padding feature is invoked (apad_xmt is set in csr4), the fcs will be appended by the pcnet-isa ii controller regardless of the state of dxmtfcs. note that the calculated fcs is transmitted most-signi?ant bit ?st. the default value of dxmtfcs is 0 after reset. transmit exception conditions exception conditions for frame transmission fall into two distinct categories; those which are the result of normal network operation, and those which occur due to abnormal network and/or host related events. normal events which may occur and which are handled autonomously by the pcnet-isa ii controller are basi- cally collisions within the slot time with automatic retry. the pcnet-isa ii controller will ensure that collisions which occur within 512 bit times from the start of trans- mission (including preamble) will be automatically retried with no host intervention. the transmit fifo en- sures this by guaranteeing that data contained within the fifo will not be overwritten until at least 64 bytes (512 bits) of data have been successfully transmitted onto the network. if 16 total attempts (initial attempt plus 15 retries) fail, the pcnet-isa ii controller sets the rtry bit in the cur- rent transmit tdte in host memory (tmd2), gives up ownership (sets the own bit to zero) for this packet, and processes the next packet in the transmit ring for transmission. iso 8802-3 (ieee/ansi 802.3) data frame preamble 1010....1010 sync 10101011 dest. addr srce. addr. length llc data pad fcs 56 bits 8 bits 6 bytes 6 bytes 2 bytes 46-1500 bytes 4 bytes 19364a-16
82 AM79C961A preliminary abnormal network conditions include: n loss of carrier n late collision n sqe test error (does not apply to 10base-t port.) these should not occur on a correctly con?ured 802.3 network, and will be reported if they do. when an error occurs in the middle of a multi-buffer frame transmission, the error status will be written in the current descriptor. the own bit(s) in the subse- quent descriptor(s) will be reset until the stp (the next frame) is found. loss of carrier a loss of carrier condition will be reported if the pcnet-isa ii controller cannot observe receive activity while it is transmitting on the aui port. after the pcnet-isa ii controller initiates a transmission, it will expect to see data ?ooped back on the di pair. this will internally generate a ?arrier sense, indicating that the integrity of the data path to and from the mau is intact, and that the mau is operating correctly. this ?arrier sense signal must be asserted before the end of the transmission. if ?arrier sense does not become active in response to the data transmission, or becomes inactive before the end of transmission, the loss of carrier (lcar) error bit will be set in tmd2 after the frame has been transmitted. the frame will not be re-tried on the basis of an lcar error. in 10base-t mode lcar will indicate that jabber or link fail state has occurred. late collision a late collision will be reported if a collision condition occurs after one slot time (512 bit times) after the trans- mit process was initiated (?st bit of preamble com- menced). the pcnet-isa ii controller will abandon the transmit process for the particular frame, set late col- lision (lcol) in the associated tmd3, and process the next transmit frame in the ring. frames experiencing a late collision will not be re-tried. recovery from this condition must be performed by upper-layer software. sqe test error during the inter packet gap time following the comple- tion of a transmitted message, the aui ci pair is asserted by some transceivers as a self-test. the inte- gral manchester encoder/decoder will expect the sqe test message (nominal 10 mhz sequence) to be returned via the ci pair within a 40 network bit time period after di pair goes inactive. if the ci inputs are not asserted within the 40 network bit time period fol- lowing the completion of transmission, then the pcnet-isa ii controller will set the cerr bit in csr0. cerr will be asserted in 10base-t mode after trans- mit if t-mau is in link fail state. cerr will never cause intr to be activated. it will, however, set the err bit in csr0. host related transmit exception conditions include buff and uflo as described in the transmit descrip- tor section. receive operation the receive operation and features of the pcnet-isa ii controller are controlled by programmable options. receive function programming automatic pad ?ld stripping is enabled by setting the astrp_rcv bit in csr4; this can provide ?xibility in the reception of messages using the 802.3 frame format. all receive frames can be accepted by setting the prom bit in csr15. when prom is set, the pcnet-isa ii controller will attempt to receive all mes- sages, subject to minimum frame enforcement. pro- miscuous mode overrides the effect of the disable receive broadcast bit on receiving broadcast frames. the point at which the bmu will start to transfer data from the receive fifo to buffer memory is controlled by the rcvfw bits in csr80. the default established during reset is 10b, which sets the threshold ?g at 64 bytes empty. automatic pad stripping during reception of an 802.3 frame the pad ?ld can be stripped automatically. astrp_rcv (bit 10 in csr4) = 1 enables the automatic pad stripping feature. the pad ?ld will be stripped before the frame is passed to the fifo, thus preserving fifo space for additional frames. the fcs ?ld will also be stripped, since it is computed at the transmitting station based on the data and pad eld characters, and will be invalid for a receive frame that has had the pad characters stripped. the number of bytes to be stripped is calculated from the embedded length eld (as de?ed in the ieee 802.3 denition) contained in the frame. the length indicates the actual number of llc data bytes con- tained in the message. any received frame which con- tains a length ?ld less than 46 bytes will have the pad ?ld stripped (if astrp_rcv is set). receive frames which have a length ?ld of 46 bytes or greater will be passed to the host unmodi?d. since any valid ethernet type ?ld value will always be greater than a normal 802.3 length ?ld ( 3 46), the pcnet-isa ii controller will not attempt to strip valid ethernet frames. note that for some network protocols the value passed in the ethernet type and/or 802.3 length ?ld is not compliant with either standard and may cause problems. the diagram below shows the byte/bit ordering of the received length ?ld for an 802.3 compatible frame format.
AM79C961A 83 preliminary ieee/ansi 802.3 frame and length field transmission order receive fcs checking reception and checking of the received fcs is per- formed automatically by the pcnet-isa ii controller. note that if the automatic pad stripping feature is enabled, the received fcs will be veri?d against the value computed for the incoming bit stream including pad characters, but it will not be passed to the host. if a fcs error is detected, this will be reported by the crc bit in rmd1. receive exception conditions exception conditions for frame reception fall into two distinct categories; those which are the result of normal network operation, and those which occur due to abnormal network and/or host related events. normal events which may occur and which are handled autonomously by the pcnet-isa ii controller are basi- cally collisions within the slot time and automatic runt packet rejection. the pcnet-isa ii controller will ensure that collisions which occur within 512 bit times from the start of reception (excluding preamble) will be automat- ically deleted from the receive fifo with no host inter- vention. the receive fifo will delete any frame which is composed of fewer than 64 bytes provided that the runt packet accept (rpa bit in csr124) feature has not been enabled. this criteria will be met regardless of whether the receive frame was the ?st (or only) frame in the fifo or if the receive frame was queued behind a previously received message. abnormal network conditions include: n fcs errors n late collision these should not occur on a correctly con?ured 802.3 network and will be reported if they do. host related receive exception conditions include miss, buff, and oflo. these are described in the receive descriptor section. preamble 1010....1010 synch 10101011 dest. addr. srce. addr. length llc data pad fcs 56 bits 8 bits 6 bytes 6 bytes 2 bytes 46?500 bytes 4 bytes most significant byte least significant byte bit 0 bit 7 start of packet at time= 0 increasing time bit 7 bit 0 45? bytes 1?500 bytes 19364a-17
84 AM79C961A preliminary magic packet operation in the magic packet mode, pcnet-isa ii completes any transmit and receive operations in progress, suspends normal activity, and enters into a state where only a magic packet could be detected. a magic packet frame is a frame that contains a data sequence which repeats the physical address (padr[47:00]) at least sixteen times frame sequentially, with bit[00] received ?st. in magic packet suspend mode, the pcnet-isa ii remains powered up. slave accesses to the pcnet-isa ii are still possible, the same as any other mode. all of the received packets are ?shed from the receive fifo. an led and/or interrupt pin could be activated, indicating the receive of a magic packet frame. this indication could be used for a variety of management tasks. magic packet mode activation this mode can be enabled by either software or exter- nal hardware means, but in either case, the mp_mode bit (csr5, bit 1) must be set ?st. hardware activation. this is done by driving the sleep pin low. deasserting the sleep pin will return the pcnet-isa ii to normal operation. software activation. this is done by setting the mp_enbl bit (csr5, bit 2). resetting this bit will return the pcnet-isa ii to normal operation. magic packet receive indicators the reception of a magic packet can be indicated either through one of the leds 1, 2 or 3, and/or the activation of the interrupt pin. mp_int bit (csr5, bit 4) will also be set upon the receive of the magic packet. led indication . either one of the leds 1, 2, or 3 could be activated by the receive of the magic packet. the ?agic packet enable bit (bit 9) in the isacsr 5, 6 or 7 should be set to enable this feature. note that the polarity of the led2 could be controlled by the ledxor bit (isacsr6, bit 14). the led could be deactivated by setting the stop bit or resetting the mp_enbl bit (csr5, bit 2). interrupt indication . interrupt pin could be activated by the receive of the magic packet. the mp_i_enbl bit (csr5, bit 3) and iena bit (csr0, bit 6) should be set to enable this feature. loopback operation loopback is a mode of operation intended for system diagnostics. in this mode, the transmitter and receiver are both operating at the same time so that the controller receives its own transmissions. the control- ler provides two types of internal loopback and three types of external loopback. in internal loopback mode, the transmitted data can be looped back to the receiver at one of two places inside the controller without actu- ally transmitting any data to the external network. the receiver will move the received data to the next receive buffer, where it can be examined by software. alterna- tively, external loopback causes transmissions to go off-chip. for the aui port, frame transmission occurs normally and assumes that an external mau will loop the frame back to the chip. for the 10base-t port, two external loopback options are available, both of which require a valid link pass state and both of which trans- mit data frames at the rj45 interface. selection of these modes is dened by the tmau_loope bit in isacsr2. one option loops the data frame back inside the chip, and is compatible with a ?ive network. the other option requires an external device (such as a ?oopback plug? to loop the data back to the chip, a function normally not available on a 10base-t network. the pcnet-isa ii chip has two dedicated fcs genera- tors, eliminating the traditional lance limitations on loopback fcs operation. the receive fcs generation logic is always enabled. the transmit fcs generation logic can be disabled (to emulate lance type loop- back operation) by setting the dxmtfcs bit in the mode register (csr15). in this con?uration, software must generate the fcs and append the four fcs bytes to the transmit frame data. the loopback facilities of the mac engine allow full operation to be veri?d without disturbance to the net- work. loopback operation is also affected by the state of the loopback control bits (loop, mendecl, and intl) in csr15. this affects whether the internal mendec is considered part of the internal or external loop- backpath. the receive fcs generation logic in the pcnet-isa ii chip is used for multicast address detection. since this fcs logic is always enabled, there are no restrictions to the use of multicast addressing while in loopback mode. when performing an internal loopback, no frame will be transmitted to the network. however, when the pcnet-isa ii controller is con?ured for internal loop- back the receiver will not be able to detect network traf?. external loopback tests will transmit frames onto the network if the aui port is selected, and the pcnet-isa ii controller will receive network traf? while con?ured for external loopback when the aui port is selected. runt packet accept is automatically enabled when any loopback mode is invoked. loopback mode can be performed with any frame size. runt packet accept is internally enabled (rpa bit in csr124 is not affected) when any loopback mode is invoked. this is to be backwards compatible to the lance (am7990) software. leds the pcnet-isa ii controllers led control logic allows programming of the status signals, which are displayed
AM79C961A 85 preliminary on 3 led outputs. one led (led0 ) is dedicated to dis- playing 10base-t link status. the status signals available are collision, jabber, receive, receive polar- ity, transmit, receive address match, and full duplex link status. if more than one status signal is enabled, they are ored together. an optional pulse stretcher is available for each programmable output. this allows emulation of the tpex (am79c98) and tpex + (am79c100) led outputs. each status signal is anded with its corresponding enable signal. the enabled status signals run to a com- mon or gate: the output from the or gate is run through a pulse stretcher, which consists of a 3-bit shift register clocked at 38 hz. the data input of the shift register is at logic 0. the or gate output asynchronously sets all three bits of the shift register when its output goes active. the output of the shift register controls the associated ledx pin. thus, the pulse stretcher provides an led output of 52 ms to 78 ms. refer to the section ?sa bus con?uration registers for information on led control via the isacsrs. signal behavior col active during collision activity on the network fdls active when full duplex operation is enabled and functioning on the selected network port jab active when the pcnet-isa ii is jabbering on the network lnkst active during link ok not active during link down rcv active while receiving data rvpol active during receive polarity is ok not active during reverse receive polarity rcvaddm active during receive with address match xmt active while transmitting data and fdls fdlse and rcvm rcvm e and xmt xmt e and rvpol rvpol e and rcv rcv e and jab jab e and col col e or to pulse stretcher and rcvaddm rcvadde 19364a-18 led control logic

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